Phase change device having two or more substantial amorphous regions in high resistance state

• US 7,701,750 B2
• Filed: 05/08/2008
• Issued: 04/20/2010
• Est. Priority Date: 05/08/2008
• Status: Active Grant

• Current Assignee: Macronix International Co., Ltd.
• Original Assignee: Macronix International Co., Ltd.
• Inventors: Shih, Yen-Hao, Lung, Hsiang-Lan, Chen, Chieh Fang
• Primary Examiner(s): LE, THONG QUOC
• Application Number:
  US12/117,164
• Publication Number:
  US 20090279349A1
• Time in Patent Office: 712 Days
• Field of Search: 365/100, 365/189.09, 365/148, 365/177, 365/196
• US Class Current: 365/148
• CPC Class Codes: H10B 63/30 comprising selection components having three or more electrodes, e.g. transistors
• CPC Class Codes: H10N 70/231 based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
• CPC Class Codes: H10N 70/826 adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
• CPC Class Codes: H10N 70/8413 adapted for resistive heating
• CPC Class Codes: H10N 70/8828 Tellurides, e.g. GeSbTe

Abstract

Memory devices are described herein along with method for operating the memory device. A memory cell as described herein includes a first electrode and a second electrode. The memory cell also comprises phase change material having first and second active regions arranged in series along an inter-electrode current path between the first and second electrode.

Claims

1. A memory device comprising:

a memory cell comprising a first electrode, a second electrode, and phase change material having first and second active regions arranged in series along an inter-electrode current path between the first electrode and the second electrode;

bias circuitry adapted to apply bias arrangements to the memory cell to store a bit, the bias arrangements including;

a first bias arrangement adapted to establish a high resistance state in the memory cell by inducing a high resistance condition in both the first and second active regions to store a first value of the bit in the memory cell, the high resistance state having a minimum resistance indicating that at least one of the active regions is in the high resistance condition, and

a second bias arrangement adapted to establish a low resistance state in the memory cell by inducing a low resistance condition in both the first and second active regions to store a second value of the bit in the memory cell, the low resistance state having a maximum resistance indicating that both the first and second active regions are in the low resistance condition; and

sense circuitry to sense the value of the bit in the memory cell by determining whether the memory cell has a resistance corresponding to the low resistance state or to the high resistance state.

2. The device of claim 1, wherein the memory cell further comprises a diode having a first terminal and a second terminal, the first active region coupled to the first terminal and the second active region coupled to the second terminal.

3. The device of claim 1, wherein the memory cell further comprises a transistor having a drain terminal and a source terminal, the first active region coupled to the drain terminal and the second active region coupled to the source terminal.

4. The device of claim 1, wherein the memory cell further comprises a bipolar junction transistor having an emitter terminal and a collector terminal, the first active region coupled to the emitter terminal and the second active region coupled to the collector terminal.

5. The device of claim 1, wherein the memory cell further comprises a bipolar junction transistor having an emitter terminal and a collector terminal, the first active region coupled to the emitter terminal, and the second active region coupled to the emitter terminal via the first active region.

6. The device of claim 1, wherein the memory cell further comprises a bipolar junction transistor having an emitter terminal and a collector terminal, the first active region coupled to the collector terminal, and the second active region coupled to the collector terminal via the first active region.

7. The device of claim 1, wherein the memory cell further comprises a transistor having a drain terminal and a source terminal, the second active region coupled to the source terminal via the first active region.

8. The device of claim 1, wherein the memory cell further comprises a transistor having a drain terminal and a source terminal, the second active region coupled to the drain terminal via the first active region.

9. The device of claim 1, wherein:

the memory cell further comprises a memory element comprising the phase change material, the first and second active regions within the memory element;

the first electrode contacting the memory element at a first contact surface, the first electrode having a width less than that of the memory element such that the first active region is adjacent the first contact surface; and

the second electrode contacting the memory element at a second contact surface, the second electrode having a width less than that of the memory element such that the second active region is adjacent the second contact surface.

10. The device of claim 1, wherein the memory cell further comprises a first memory element comprising a portion of the phase change material and a second memory element comprising a portion of the phase change material, the first active region within the first memory element and the second active region within the second memory element.

11. The device of claim 10, wherein:

the first memory element contacts the first electrode;

the second memory element contacts the second electrode; and

the memory cell further comprises an inner electrode arranged along the inter-electrode current path between the first and second memory elements.

12. The device of claim 11, wherein:

the inner electrode contacts the first memory element at a first contact surface and contacts the second memory element at a second contact surface;

the first memory element has a width greater than that of the inner electrode such that the first active region is adjacent the first contact surface; and

the second memory element has a width greater than that of the inner electrode such that the second active region is adjacent the second contact surface.

13. The device of claim 11, wherein:

the first electrode contacts the first memory element at a first contact surface, the first electrode having a width less than that of the first memory element such that the first active region is adjacent the first contact surface;

the memory cell further comprises a conductive electrode on the first memory element, the conductive electrode having a width greater than that of the first electrode;

the inner electrode on the conductive electrode and contacting the second memory element at a second contact surface, the inner electrode having a width less than that of the conductive electrode such that the second active region is adjacent the second contact surface.

14. The device of claim 1, wherein the first and second active regions are located in the same plane.

15. The device of claim 1, wherein the first active region overlies the second active region.

16. The device of claim 1, wherein the memory cell further comprises a diode having a first terminal and a second terminal, the first active region coupled to the first terminal via the second active region.

17. A method for operating a memory cell comprising a first electrode, a second electrode, and phase change material having first and second active regions arranged in series along an inter-electrode current path between the first electrode and the second electrode, the method comprising:

determining a data value of a bit to be stored in the memory cell;

applying a first bias arrangement to the memory cell if the data value is a first value, the first bias arrangement adapted to establish a high resistance state in the memory cell by inducing a high resistance condition in both the first and second active regions to store the first value of the bit, the high resistance state having a minimum resistance indicating that at least one of the active regions is in the high resistance condition;

applying a second bias arrangement to the memory cell if the data value is a second value, the second bias arrangement adapted to establish a low resistance state in the memory cell by inducing a low resistance condition in both the first and second active regions to store the second value of the bit, the low resistance state having a maximum resistance indicating that both the first and second active regions are in the low resistance state; and

determining the data value of the bit stored in the memory cell by determining whether the memory cell has a resistance corresponding to the low resistance state or to the high resistance state.

18. The method of claim 17, wherein the determining the data value of the bit stored in the memory cell comprises applying a third bias arrangement to the memory cell and detecting a current in the memory cell, the current in the memory cell corresponding to the data value of the bit stored in the memory cell.

19. The method of claim 17, wherein the memory cell further comprises a diode having a first terminal and a second terminal, the first active region coupled to the first terminal and the second active region coupled to the second terminal.

20. The method of claim 17, wherein the memory cell further comprises a transistor having a drain terminal and a source terminal, the first active region coupled to the drain terminal and the second active region coupled to the source terminal.

21. The method of claim 17, wherein the memory cell further comprises a bipolar junction transistor having an emitter terminal and a collector terminal, the first active region coupled to the emitter terminal and the second active region coupled to the collector terminal.

22. The method of claim 17, wherein the memory cell further comprises a transistor having a drain terminal and a source terminal, the second active region coupled to the source terminal via the first active region.

23. The method of claim 17, wherein the memory cell further comprises a transistor having a drain terminal and a source terminal, the first active region coupled to the source terminal and the second active region coupled to the source terminal.

24. The method of claim 17, wherein the memory cell further comprises a bipolar junction transistor having an emitter terminal and a collector terminal, the first active region coupled to the emitter terminal, and the second active region coupled to the emitter terminal via the first active region.

25. The method of claim 17, wherein the memory cell further comprises a bipolar junction transistor having an emitter terminal and a collector terminal, the first active region coupled to the collector terminal, and the second active region coupled to the collector terminal via the first active region.

26. The method of claim 17, wherein the memory cell further comprises a diode having a first terminal and a second terminal, the first active region coupled to the first terminal via the second active region.