Read, verify word line reference voltage to track source level

• US 7,701,761 B2
• Filed: 12/20/2007
• Issued: 04/20/2010
• Est. Priority Date: 12/20/2007
• Status: Expired due to Fees

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Corporation (Western Digital Corporation)
• Inventors: Pan, Feng, Pham, Trung, Woo, Byungki
• Primary Examiner(s): Nguyen; Viet Q
• Application Number:
  US11/961,917
• Publication Number:
  US 20090161434A1
• Time in Patent Office: 852 Days
• Field of Search: 365/185.02, 365/185.22, 365/185.21, 365/185.09, 365/185.15, 365/189.07
• US Class Current: 365/185.02
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 16/30 Power supply circuits

Abstract

A non-volatile memory device has individual pages of memory cells to be sensed in parallel. The memory device includes a source level tracking circuit coupled to receive a predetermined word line voltage from a word line voltage supply and the voltage level at the aggregate source node of one or more pages and coupled to provide to word lines of the memory an output voltage during the sensing operation, where the source level tracking circuit includes an op amp whereby the output voltage is the word line voltage offset by an amount to track the voltage level at the aggregate node and compensate for source bias errors due to a finite resistance in the ground loop.

Claims

1. In a non-volatile memory device having individual pages of memory cells to be sensed in parallel, each memory cell having a source, a drain, a charge storage unit and a control gate for controlling a conduction current along said drain and source, the memory device comprising:

a page source line coupled to the source of each memory cell in a page;

an aggregate node coupled to individual page source lines;

a source voltage control circuit coupled via said aggregate node to a page source line of a selected page for memory operation;

a word line coupling to the control gate of each memory cell of said page;

a word line voltage supply for providing a predetermined word line voltage; and

a source level tracking circuit connectable to receive the word line voltage and the voltage level at the aggregate node and connectable to provide to the word line an output voltage during the sensing operation, including an op amp with an output providing the output voltage and having a first input connected to receive a voltage derived from the word line voltage and the aggregate node voltage and having a second input connected by a feedback loop from the output.

2. The non-volatile memory device of claim 1, wherein the source level tracking circuit further comprises:

a first resistive element and a second resistive element connected in series between the word line voltage and the voltage level at the aggregate node, wherein the first input is connected via a node between the first and second resistive elements.

3. The non-volatile memory device of claim 2, wherein the source level tracking circuit further comprises:

a third resistive element and a fourth resistive element connected in series between the output and ground, wherein the second input is connected via a node between the third and fourth resistive elements.

4. The non-volatile memory device of claim 3, wherein the first, second, third and fourth resistive elements are formed to have essentially equal resistance values.

5. The non-volatile memory device of claim 3, wherein the first, second, third and fourth resistive elements are formed so that they do not all have essentially equal resistance values.

6. The non-volatile memory device of claim 1, wherein the source level tracking circuit further comprises:

a first capacitive element and a second capacitive element connected in series between the word line voltage and the voltage level at the aggregate node, wherein the first input is connected via a node between the first and second resistive elements; and

a third capacitive element and a fourth capacitive element connected in series between the output and ground, wherein the second input is connected via a node between the third and fourth resistive elements.

7. The non-volatile memory device of claim 1, wherein output voltage is equal to the sum of word line voltage and a predetermined proportion of the voltage level at the aggregate node.

8. The non-volatile memory device of claim 7, wherein output voltage is equal to the sum of word line voltage and the voltage level at the aggregate node.

9. The non-volatile memory device of claim 1, wherein the sensing operation is a read operation.

10. The non-volatile memory device of claim 1, wherein the sensing operation is a verify operation.

11. The non-volatile memory device of claim 1, wherein the predetermined word line voltage includes temperature compensation.