Leakage compensation during program and read operations

• US 7,701,763 B2
• Filed: 04/23/2008
• Issued: 04/20/2010
• Est. Priority Date: 04/23/2008
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Roohparvar, Frankie F.
• Primary Examiner(s): AUDUONG, GENE NGHIA
• Application Number:
  US12/108,148
• Publication Number:
  US 20090268520A1
• Time in Patent Office: 727 Days
• Field of Search: 365/185.09, 365/185.17, 365/185.22, 365/185.23, 365/185.24, 365/185.25
• US Class Current: 365/185.09
• CPC Class Codes: G11C 11/5621 using charge storage in a floating gate
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 27/005 with non-volatile charge storage, e.g. on floating gate or MNOS

Abstract

Methods of operating a memory and a memory are disclosed, such as an analog non-volatile memory device and process that reduces the effects of charge leakage from data cache capacitors, maintaining stored charge levels as data. In one embodiment, data values are compensated for leakage that is uniform across the data cache by charging a reference capacitor or initiating another leakage model and uniformly adjusting the ground of the data capacitors by the effect amount or by adjusting an amplifier offset or gain. In another embodiment, held data values are compensated for charge leakage effects that are non-uniform due to data values being sequentially transferred into the data cache by scaling a ground node or adjustment of amplifier offset/gain of each capacitor in the data cache against the leakage reference and the order in which data was transferred into the data cache.

Claims

1. A method of operating a memory, comprising:

estimating a charge loss using a charge leakage model;

storing a plurality of voltages in a plurality of storage devices in a data cache of a memory; and

compensating the plurality of storage devices for charge loss at least partially based on the estimated charge loss.

2. The method of claim 1, wherein the storage devices are capacitances.

3. The method of claim 2, wherein the capacitances comprise capacitors.

4. The method of claim 1, wherein the charge leakage model is one of a reference capacitor and a timer.

5. The method of claim 1, wherein compensating the plurality of storage devices further comprises adjusting a ground reference node coupled to the storage devices of the data cache.

6. The method of claim 1, wherein compensating the plurality of storage devices further comprises adjusting one of an offset and a gain of amplifiers coupled to each storage device of the plurality of storage devices of the data cache.

7. The method of claim 1, wherein compensating the plurality of storage devices further comprises adjusting at least partially based on the data pattern.

8. The method of claim 1, compensating the plurality of storage devices further comprises amplifying and/or buffering.

9. A non-volatile memory, comprising:

a non-volatile memory array having a plurality of non-volatile memory cells;

a data cache having a plurality of storage devices; and

a charge leakage model;

wherein the non-volatile memory is adapted to compensate the plurality of storage devices for uniform charge loss at least partially based on an output of the charge leakage model by,

estimating a charge loss using the charge leakage model,

storing a plurality voltages in the plurality of storage devices of the data cache, and

compensating the plurality of analog storage devices for charge loss at least partially based on the charge leakage model.

10. The non-volatile memory of claim 9, wherein the data cache further comprises sample and hold circuitry.

11. The non-volatile memory of claim 9, wherein the charge leakage model is one of a reference capacitor and a timer.

12. The non-volatile memory of claim 9, wherein the memory is adapted to compensate the plurality of storage devices at least partially based on the charge leakage model by one of uniformly adjusting a ground node coupled to the storage devices of the data cache to compensate for charge loss, and non-uniformly adjusting a ground node coupled to each separate storage device of the plurality of storage devices of the data cache to compensate for charge loss.

13. The non-volatile memory of claim 9, wherein the memory is adapted to compensate the plurality of storage devices at least partially based on the charge leakage model by one of uniformly adjusting an amplifier offset or an amplifier gain of an amplifier coupled to each analog storage device of the plurality of storage devices of the data cache, and non-uniformly adjusting an amplifier offset or an amplifier gain of an amplifier coupled to each analog storage device of the plurality of storage devices of the data cache to compensate for charge loss.

14. A method of operating a memory, comprising:

initiating a charge leakage model;

transferring a plurality of voltages to a memory and storing them in a plurality of storage devices of a data cache of the memory; and

compensating the plurality of storage devices for non-uniform charge loss at least partially based on an output of the charge leakage model.

15. The method of claim 14, wherein the data cache further comprises capacitive sample and hold circuitry.

16. The method of claim 14, wherein compensating the plurality of storage devices for non-uniform charge loss at least partially based on an output of the charge leakage model further comprises compensating the plurality of storage devices for non-uniform charge loss adjusting by a scaled amount at least partially based on an output of the charge leakage model in an order in which the voltages are transferred.

17. The method of claim 14, wherein transferring a plurality of voltages to a memory and storing them in a plurality of storage devices of a data cache of the memory further comprises sequentially transferring a plurality of voltages to a memory and storing them in a plurality of storage devices of a data cache of the memory.

18. The method of claim 14, wherein further comprising adjusting a separate ground node coupled to each storage device of the data cache to compensate for non-uniform charge loss across the data cache wherein each ground node is coupled to a separate tap of one of a voltage divider, a resistive ladder, and a graduated resistance path of a leakage adjustment circuit.

19. A non-volatile memory, comprising:

a non-volatile memory array having a plurality of non-volatile memory cells;

a data cache having a plurality of storage devices; and

a charge leakage model;

wherein the non-volatile memory is adapted to compensate the plurality of storage devices of a data cache of the non-volatile memory at least partially based on an output of the charge leakage model by,

initiating the charge leakage model,

transferring a plurality of voltages to a memory and storing them in the plurality of storage devices of the data cache, and

compensating the plurality of storage devices for charge loss at least partially based on an output of the charge leakage model.

20. The non-volatile memory of claim 19, wherein the memory is adapted to initiate the charge leakage model by charging a reference capacitor or activating a timer.

21. The non-volatile memory of claim 19, wherein the memory is adapted to initiate the charge leakage model at one of the start of voltage transfer to the memory, the start of sequential voltage transfer to the memory, after transfer of voltages is complete.

22. The non-volatile memory of claim 19, wherein the plurality of storage devices each have an associated buffer amplifier.

23. A method of operating a memory, comprising:

initiating a memory operation;

initiating a charge leakage model;

transferring a plurality of voltages to a memory and storing them in a plurality of storage devices of a data cache of the memory; and

compensating the plurality of storage devices for charge loss at least partially based on an output of the charge leakage model while executing the memory operation in the memory.

24. The method of claim 23, wherein initiating a memory operation further comprises one of receiving an external memory command and internally initiating a memory operation in the memory.

25. The method of claim 23, wherein compensating the plurality of storage devices for charge loss at least partially based on an output of the charge leakage model while executing the memory operation in the memory further comprises compensating the plurality of storage devices for one of uniform charge loss, non-uniform charge loss, and voltage level based charge loss while executing the memory operation in the memory.