Two levels of voltage regulation supplied for logic and data programming voltage of a memory device

• US 7,701,797 B2
• Filed: 03/30/2007
• Issued: 04/20/2010
• Est. Priority Date: 05/15/2006
• Status: Expired due to Fees

• Current Assignee: Apple Inc.
• Original Assignee: Apple Inc.
• Inventors: Cornwell, Michael J., Dudte, Christopher P.
• Primary Examiner(s): Nguyen; Dang T
• Application Number:
  US11/694,763
• Publication Number:
  US 20070263469A1
• Time in Patent Office: 1,117 Days
• Field of Search: 365/226, 365/185.17, 365/185.18, 365/189.09, 365/185.33, 365/189.01, 365/189.08, 365/185.11, 365/185.09, 365/189.04
• US Class Current: 365/226
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/30 Power supply circuits
• CPC Class Codes: G11C 2211/5641 Multilevel memory having cells with different number of storage levels
• CPC Class Codes: G11C 5/145 Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor G11C5/141 takes precedence

Abstract

Systems and methods involve the use of a flash memory device having multiple flash memory cells. A first interface is adapted to receive power for selectively programming each flash memory cell. A second interface is adapted to receive power supplied to logic level circuitry to perform the selection of flash memory cells to be supplied with power from the first input during a write operation.

Claims

1. A flash memory device comprising:

a flash memory die including;

a plurality of flash memory cells;

a first interface for receiving power for selectively programming each flash memory cell;

a second interface for receiving power supplied to logic level circuitry to perform the selection of flash memory cells to be supplied with power from the first input during a write operation;

a first power source external to the flash memory die adapted to provide programming power to the first interface, wherein the first power source is coupled to a plurality of flash memory dies, each flash memory die including a plurality of flash memory cells; and

a second power source external to the flash memory die adapted to provide logic-level power to the second interface, wherein the second power source is different than the first power source.

2. The flash memory device of claim 1, wherein the second interface further supplies power to the logic level circuitry for selecting flash memory cells during a read operation.

3. The flash memory device of claim 1, wherein the plurality of memory cells comprise NAND flash memory cells.

4. The flash memory device of claim 1, wherein the plurality of memory cells comprise NOR flash memory cells.

5. The flash memory device of claim 1, wherein the first interface is adapted to receive a voltage within a range of approximately 12 to 20 volts.

6. The flash memory device of claim 1, wherein the second interface is adapted to receive a voltage within a range of approximately 1 to 3 volts.

7. The flash memory device of claim 1, wherein each memory cell is adapted to receive a charge to a voltage representing a data value having more than 4 bits.

8. The flash memory device of claim 1, wherein the second power source is coupled to a plurality of flash memory dies, each flash memory die including a plurality of flash memory cells.

9. The flash memory device of claim 1, further comprising:

a controller to control access to the flash memory die by controlling the second power source.

10. The flash memory device of claim 1, further comprising:

a flash disk controller external to the flash memory die for controlling access to the flash memory cells, the flash disk controller coupled to the first power source and the second power source to provide the power to the first interface and the second interface.