Digital architecture for radio-frequency apparatus and associated methods

• US 7,702,362 B2
• Filed: 11/28/2005
• Issued: 04/20/2010
• Est. Priority Date: 01/12/2001
• Status: Expired due to Term

• Current Assignee: Silicon Laboratories Incorporated
• Original Assignee: Silicon Laboratories Incorporated
• Inventors: Srinivasan, Vishnu S., Spurbeck, Mark S., Paulus, Tod, Scott, Jeffrey W., Tuttle, G. Tyson, Behrens, Richard T., Vishakhadatta, G. Diwakar, Kerth, Donald A.
• Primary Examiner(s): LEE, JOHN J
• Application Number:
  US11/287,995
• Publication Number:
  US 20060141973A1
• Time in Patent Office: 1,604 Days
• Field of Search: 455/553.1, 455/76, 455/88, 455/73, 455/313, 455/74, 455/552.1, 455/77, 455/86, 455/114.2, 455/303, 455/147, 455/306, 455/307, 455/311, 455/550.1, 455/127.4, 455/165.1, 375/219, 375/316, 375/346, 370/350
• US Class Current: 455/553.1
• CPC Class Codes: H04B 1/0003 Software-defined radio [SDR] systems, i.e. systems wherein components typically implemented in hardware, e.g. filters or modulators/demodulators, are implented using software, e.g. by involving an AD or DA conversion stage such that at least part of the signal processing is performed in the digital domain digital baseband systems H04L25/00; digital modulation/demodulation H04L27/00; CDMA H04B1/707; TDMA H04B7/2643; image transmission H04N5/00
• CPC Class Codes: H04B 1/28 the receiver comprising at least one semiconductor device having three or more electrodes
• CPC Class Codes: H04B 1/38 Transceivers, i.e. devices in which transmitter and receiver form a structural unit and in which at least one part is used for functions of transmitting and receiving
• CPC Class Codes: H04B 1/406 with more than one transmission mode, e.g. analog and digital modes
• CPC Class Codes: H04B 15/02 Reducing interference from electric apparatus by means located at or near the interfering apparatus
• CPC Class Codes: H04B 15/04 the interference being caused by substantially sinusoidal oscillations, e.g. in a receiver or in a tape-recorder
• CPC Class Codes: H04B 2215/064 Reduction of clock or synthesizer reference frequency harmonics

Abstract

A radio-frequency (RF) receiver includes a receiver analog circuitry and a receiver digital circuitry. The receiver analog circuitry resides within a first integrated circuit and the receiver digital circuitry resides within a second integrated circuit. The second integrated circuit couples to the first integrated circuit via a one-bit digital interface. The receiver analog circuitry receives an RF signal and processes the received RF signal to generate a digital signal. The receiver analog circuitry provides the digital signal to the receiver digital circuitry. The receiver digital circuitry includes a digital down-converter circuitry that mixes the digital signal with an intermediate frequency (IF) local oscillator (LO) signal to generate a digital down-converted signal. The receiver digital circuitry also includes a digital filter circuitry that filters the digital down-converted signal to generate a filtered digital signal.

Claims

1. A radio-frequency (RF) apparatus, comprising:

a first circuit partition, comprising;

an amplifier that receives an RF signal, and provides an amplified RF signal;

a down-converter that mixes the amplified RF signal to generate a down-converted signal; and

an analog-to-digital converter that converts the down-converter signal to a digital signal; and

a second circuit partition, comprising;

a digital down-converter that converts the digital signal to generate a baseband signal;

a digital channelization filter that filters the baseband signal to generate a filtered baseband signal; and

a digital programmable-gain amplifier that amplifies the filtered baseband signal, using a prescribed gain.

2. The radio-frequency (RF) apparatus according to claim 1, wherein the analog-to digital converter provides the digital signal as a one-bit digital signal.

3. The radio-frequency (RF) apparatus according to claim 1, wherein the first and second circuit partitions are isolated from each other.

4. The radio-frequency (RF) apparatus according to claim 1, wherein each of the first and second circuit partitions comprises a thin-film module.

5. The radio-frequency (RF) apparatus according to claim 1, wherein each of the first and second circuit partitions comprises a thick-film module.

6. The radio-frequency (RF) apparatus according to claim 1, wherein each of the first and second circuit partitions comprises a module.

7. The radio-frequency (RF) apparatus according to claim 1, wherein the first and second circuit partitions are part of a low-intermediate-frequency (low-IF) receiver.

8. A digital receive-path circuit in a radio-frequency (RF) apparatus, the digital receive-path circuit comprising:

an interface circuit that receives a complex one-bit digital signal;

a digital down-converter that mixes the complex one-bit digital signal with a complex digital intermediate frequency (IF) local oscillator signal to generate a complex digital down-converted signal;

a cascaded integrator/comb (CIC) filter that filters the complex digital down-converted signal to generate a first filtered complex digital signal;

an infinite-impulse-response (JIR) filter that filters the first filtered complex digital signal to generate a second filtered complex digital signal; and

a notch filter that removes a residual direct-current (DC) offset from the second filtered complex digital signal.

9. The digital receive-path circuit according to claim 8, wherein the interface circuit further comprises an interface controller.

10. The digital receive-path circuit according to claim 8, wherein the digital down-converter comprises a plurality of multipliers.

11. The digital receive-path circuit according to claim 8, further comprising a digital IF local oscillator circuit that supplies the complex digital IF local oscillator signal.

12. The digital receive-path circuit according to claim 8, wherein the CIC filter comprises a decimator circuit, and a plurality of delay circuits.

13. The digital receive-path circuit according to claim 8, wherein the IIR filter comprises a plurality of biquad circuits.

14. The digital receive-path circuit according to claim 8, wherein the notch filter comprises a plurality of delay circuits, and a plurality of combiner circuits.

15. The digital receive-path circuit according to claim 8, wherein the notch filter comprises a complex band-pass filter circuitry arranged within a feedback loop.

16. A method of processing a radio-frequency (RF) signal, the method comprising:

amplifying the RF signal within a first circuit partition to generate an amplified RF signal;

mixing the amplified RF signal within the first circuit partition to generate a down-converted signal;

converting, within the first circuit partition, the down-converted signal to a digital signal;

supplying the digital signal to a second circuit partition;

converting the digital signal to a baseband signal within a second circuit partition;

digital channelization filtering the baseband signal within the second circuit partition; and

digitally amplifying the filtered baseband signal within the second circuit partition, using a programmable gain.

17. The method according to claim 16, wherein the digital signal comprises a one-bit signal.

18. The method according to claim 16, wherein the first and second circuit partitions are isolated from one another.

19. The method according to claim 16, wherein each of the first and second circuit partitions comprises a module.

20. The method according to claim 16, wherein the first and second circuit partitions are part of a low-intermediate-frequency (low-IF) receiver.