Random number generation circuit
First Claim
1. A random number generation circuit, comprising:
- a ring oscillator which has odd number of inverting amplifiers connected in ring shape;
a delay control circuit which generates a predetermined clock signal by delaying a reference clock signal;
a first sampling circuit which samples an oscillation signal generated by the ring oscillator with the predetermined clock signal;
a first logical equalization circuit which equalizes occurrence frequency of “
0” and
“
1”
of a sampling signal sampled by the first sampling circuit;
a linear feedback shift register (LFSR) which generates random serial data based on an output signal of the first logical equalization circuit; and
a serial-parallel converter which generates random parallel data used for controlling a delay amount of the delay control circuit by converting the random serial data from serial to parallel.
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Accused Products
Abstract
A random number generation circuit has a ring oscillator which has odd number of inverting amplifiers connected in ring shape, a delay control circuit which generates a predetermined clock signal by delaying a reference clock signal, a first sampling circuit which samples an oscillation signal generated by the ring oscillator with the predetermined clock signal, a first logical equalization circuit which equalizes occurrence frequency of “0” and “1” of a sampling signal sampled by the first sampling circuit, a linear feedback shift register (LFSR) which generates random serial data based on an output signal of the first logical equalization circuit, and a serial-parallel converter which generates random parallel data used for controlling a delay amount of the delay control circuit by converting the random serial data from serial to parallel.
20 Citations
20 Claims
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1. A random number generation circuit, comprising:
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a ring oscillator which has odd number of inverting amplifiers connected in ring shape; a delay control circuit which generates a predetermined clock signal by delaying a reference clock signal; a first sampling circuit which samples an oscillation signal generated by the ring oscillator with the predetermined clock signal; a first logical equalization circuit which equalizes occurrence frequency of “
0” and
“
1”
of a sampling signal sampled by the first sampling circuit;a linear feedback shift register (LFSR) which generates random serial data based on an output signal of the first logical equalization circuit; and a serial-parallel converter which generates random parallel data used for controlling a delay amount of the delay control circuit by converting the random serial data from serial to parallel. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A random number generation circuit, comprising:
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a ring oscillator which has odd number of inverting amplifiers connected in ring shape and odd number of current amplification circuits connected to current paths of the respective inverting amplifiers; a first sampling circuit which samples an oscillation signal generated by the ring oscillator with a predetermined clock signal; a first logical equalization circuit which equalizes occurrence frequency of “
0” and
“
1”
of a sampling signal sampled by the first sampling circuit;a linear feedback shift register (LFSR) which generates random serial data based on an output signal of the first logical equalization circuit; and a serial-parallel converter which generates random parallel data by converting the random serial data from serial to parallel. - View Dependent Claims (10, 11, 12, 13, 14)
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15. A random number generation circuit, comprising:
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a ring oscillation type VCO which has odd number of inverting amplifiers connected in ring shape and odd number of voltage control circuits configured to perform voltage control of drive capability of the odd number of inverting amplifiers; a first sampling circuit which samples an oscillation signal generated by the ring oscillation type VCO with a predetermined clock signal; a first logical equalization circuit which equalizes occurrence frequency of “
0” and
“
1”
of a sampling signal sampled by the first sampling circuit;a linear feedback shift register which generates random serial data based on an output signal of the first logical equalization circuit; and a serial-parallel converter which generates random parallel data by converting the random serial data from serial to parallel. - View Dependent Claims (16, 17, 18, 19, 20)
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Specification