Hybrid mapping implementation within a non-volatile memory system

• US 7,702,880 B2
• Filed: 12/28/2006
• Issued: 04/20/2010
• Est. Priority Date: 10/01/2003
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Corporation (Western Digital Corporation)
• Inventors: Qawami, Bahman, Sabet-Sharghi, Farshid, Chang, Robert C.
• Primary Examiner(s): PATEL, HETUL B
• Application Number:
  US11/617,441
• Publication Number:
  US 20070150694A1
• Time in Patent Office: 1,209 Days
• Field of Search: 711/202
• US Class Current: 711/202
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory

Abstract

Methods and apparatus for allowing different mapping implementations, including a many-to-one logical to physical block mapping, to be used within a memory system are disclosed. According to one aspect of the present invention, a method for mapping a plurality of logical blocks to a physical block includes identifying a first logical block meets at least one criterion. The method also includes identifying a second logical block which is substantially complementary to the first logical block, and providing contents associated with the first logical block and contents associated with the second logical block to the physical block.

Claims

1. A method for mapping logical blocks with physical blocks in a non-volatile memory system, wherein a plurality of the logical blocks in the non-volatile memory system each include a plurality of logical pages organized into at least two logical block groups, the method comprising:

determining whether a first physical block in the non-volatile memory system is logically associated with one or more logical block groups of a first logical block in the non-volatile memory system;

determining whether it is appropriate to logically map one or more logical block groups of a second logical block in the non-volatile memory system to the first physical block responsive to determining that the first physical block is logically associated with the one or more logical block groups of the first logical block; and

logically mapping the one or more logical block groups of the second logical block to the first physical block responsive to determining that it is appropriate to map the one or more logical block groups of the second logical block to the first physical block; and

wherein the one or more logical block groups of the first logical block and the one or more logical block groups of the second logical block are concurrently mapped to the first physical block.

2. The method of claim 1, further comprising:

logically mapping the one or more logical block groups of the second logical block to the first physical block responsive to determining that the first physical block is not logically associated with the one or more logical block groups of the first logical block.

3. The method of claim 2 further comprising:

determining whether it is appropriate to logically map one or more logical block groups of a third logical block to the first physical block; and

logically mapping the one or more logical block groups of the third logical block to the first physical block responsive to determining that it is appropriate to logically map the one or more logical block groups of the third logical block to the first physical block, wherein the one or more logical block groups of the second logical block and the one or more logical block groups of the third logical block are concurrently mapped to the first physical block.

4. The method of claim 2 wherein logically mapping the one or more logical block groups of the second logical block to the first physical block includes storing contents associated with the second logical block into the first physical block.

5. The method of claim 2 further comprising:

determining whether it is appropriate to logically map the one or more logical block groups of the second logical block to a second physical block; and

logically mapping the one or more logical block groups of the second logical block to the second physical block responsive to determining that it is appropriate to logically map the one or more logical block groups of the second logical block to the second physical block.

6. The method of claim 1, wherein determining whether it is appropriate to logically map the one or more logical block groups of the second logical block to the first physical block is dependent on how many of the one or more logical block groups of the second logical block are logically associated with any physical blocks.

7. The method of claim 1, wherein determining whether it is appropriate to logically map the one or more logical block groups of the second logical block to the first physical block comprises determining a number of the one or more logical block groups of the second logical block that are logically associated with any physical blocks.

8. The method of claim 7, wherein determining whether it is appropriate to logically map the one or more logical block groups of the second logical block to the first physical block further comprises comparing the number of the one or more logical block groups of the second logical block that are logically associated with any physical blocks with a predetermined number.

9. The method of claim 8, wherein it is determined that it is appropriate to logically map the one or more logical block groups of the second logical block to the first physical block based on the comparison of the number of the one or more logical block groups of the second logical block that are logically associated with any physical blocks with the predetermined number.

10. A non-volatile memory system comprising:

a non-volatile memory, the non-volatile memory including a plurality of physical blocks, and a plurality of logical blocks each having a plurality of pages organized into at least two logical block groups;

means for determining whether a first physical block is logically associated with one or more logical block groups of a first logical block;

means for determining whether it is appropriate to logically map one or more logical block groups of a second logical block to the first physical block responsive to determining that the first physical block is logically associated with the one or more logical block groups of the first logical block; and

means for logically mapping the one or more of the logical block groups of the second logical block to the first physical block responsive to determining that it is appropriate to logically map the one or more logical block groups of the second logical block to the first physical block, wherein the one or more logical block groups of the first logical block and the one or more logical block groups of the second logical block are concurrently mapped to the first physical block.

11. The non-volatile memory system of claim 10 wherein the non-volatile memory system further comprises:

means for logically mapping the one or more of the logical block groups of the second logical block to the first physical block responsive to determining that the first physical block is not logically associated with the logical block groups of the first logical block.

12. The non-volatile memory system of claim 11 wherein the means for logically mapping the one or more logical block groups of the first logical block to a second physical block include means for storing contents associated with the second logical block into the first physical block.

13. The non-volatile memory system of claim 11 further comprising:

means for determining whether it is appropriate to logically map the one or more logical block groups of the second logical block to a second physical block; and

means for logically mapping the one or more logical block groups of the second logical block to the second physical block responsive to determining that it is appropriate to logically map the one or more logical block groups of the second logical block to the second physical block.

15. The non-volatile memory system of claim 10 wherein the non-volatile memory system is one of an embedded system, a Smart Media card, a Compact Flash card, a Secure Digital Card, and a MultiMedia card.

16. The non-volatile memory system of claim 10 means for determining whether it is appropriate to logically map one or more logical block groups of the second logical block to the first physical block include means for determining how many of the one or more logical block groups of the second logical block are logically associated with any physical blocks.

14. The non-volatile memory system of 10 further comprising:

means for determining whether it is appropriate to logically map one or more logical block groups of a third logical block to the first physical block; and

means for logically mapping the one or more logical block groups of the third logical block to the first physical block responsive to determining that it is appropriate to logically map the one or more logical block groups of the third logical block to the first physical block, wherein the one or more logical block groups of the first logical block the one or more logical block groups of the second logical block, and the one or more logical block groups of the third logical block are concurrently mapped to the first physical block.

17. A memory system comprising:

a non-volatile memory, the non-volatile memory having a plurality of physical blocks, the non-volatile memory further having a plurality of logical blocks each having a plurality of logical pages organized into at least two logical block groups;

code devices operating to determine whether a first physical block is logically associated with one or more logical block groups of a first logical block;

code devices operating to determine whether it is appropriate to logically map one or more logical block groups of a second logical block to the first physical block responsive to determining that the first physical block is logically associated with the one or more logical block groups of the first logical block;

code devices operating to logically map the one or more logical block groups of the second logical block to the first physical block responsive to determining that it is appropriate to logically map the one or more logical block groups of the second logical block to the first physical block; and

a memory area that stores at least a portion of the code devices for execution by a controller;

wherein the code devices cooperate so that the one or more logical block groups of the first logical block and the one or more logical block groups of the second logical block may be concurrently mapped to the first physical block.

18. The memory system of claim 17 wherein the memory system further comprises:

code devices operating to logically map the one or more logical block groups of the second logical block to the first physical block responsive to determining that the first physical block is not logically associated with the one or more logical block groups of the first logical block.

19. The memory system of claim 18 further comprising:

code devices operating to determine whether it is appropriate to logically map one or more logical block groups of a third logical block to the first physical block; and

code devices operating to logically map the one or more logical block groups of the third logical block to the first physical block responsive to determining that it is appropriate to logically map the one or more logical block groups of the third logical block to the first physical block, wherein the one or more logical block groups of the second logical block and the one or more block groups of the third logical block are concurrently mapped to the first physical block.

20. The memory system of claim 17 further including:

code devices operating to determine whether it is appropriate to logically map one or more logical block groups of the second logical block to a second physical block; and

code devices operating to logically map the one or more logical block groups of the second logical block to the second physical block responsive to determining that it is appropriate to logically map the one or more logical block groups of the second logical block to the second physical block.

21. The memory system of claim 17 wherein the non-volatile memory system is one of an embedded system, a Smart Media card, a Compact Flash card, a Secure Digital Card, and a Multimedia card.

22. The memory system of claim 17 wherein code devices operating to determine whether it is appropriate to logically map one or more logical block groups of the second logical block to the first physical block is dependent on how many of the one or more logical block groups of the second logical block are logically associated with any physical blocks.