Shared interrupt control method and system for a digital signal processor
First Claim
1. A method for processing interrupts arising in a multithreaded processor, comprising the steps of:
- receiving in an interrupt register a plurality of interrupts, each of the plurality of interrupts corresponding to an external interrupt of a statistically indeterminate interrupt type;
associating a plurality of processing threads with said interrupt register for receiving at least one of said plurality of interrupts from said interrupt register;
determining, for each of the plurality of processing threads, that the processing thread can take one of the plurality of interrupts if the processing thread has enabled interrupt processing and the processing thread is not an exception handler configured to handle internal exceptions; and
masking, based on the determining step, at least a subset of said plurality of processing threads so as to receive within each of said threads within said subset only ones of said plurality of interrupts of one or more predetermined types and exclude from each of said threads within said subset ones of said plurality of interrupts of a different one or more predetermined types,wherein the statistically indeterminate interrupt type of the received plurality of interrupts is determined from the masking step, thereby controlling on a per thread basis the processing of said plurality of interrupts according to the mask associated with a particular thread.
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Accused Products
Abstract
Techniques for the design and use of a digital signal processor, including (but not limited to) processing transmissions in a communications (e.g., CDMA) system. The disclosed method and system process interrupts arising in a multithreaded processor by receiving in an interrupt register a plurality of interrupts of a statistically indeterminate interrupt type and then associating a plurality of processing threads with the interrupt register for receiving the interrupt from the interrupt register. The method and system mask at least a subset of the plurality of processing threads so as to receive within each of the threads within the subset only ones of the plurality of interrupts of one or more predetermined types, thereby controlling on a per thread basis the processing of the plurality of interrupts according to the mask associated with a particular thread.
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Citations
26 Claims
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1. A method for processing interrupts arising in a multithreaded processor, comprising the steps of:
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receiving in an interrupt register a plurality of interrupts, each of the plurality of interrupts corresponding to an external interrupt of a statistically indeterminate interrupt type; associating a plurality of processing threads with said interrupt register for receiving at least one of said plurality of interrupts from said interrupt register; determining, for each of the plurality of processing threads, that the processing thread can take one of the plurality of interrupts if the processing thread has enabled interrupt processing and the processing thread is not an exception handler configured to handle internal exceptions; and masking, based on the determining step, at least a subset of said plurality of processing threads so as to receive within each of said threads within said subset only ones of said plurality of interrupts of one or more predetermined types and exclude from each of said threads within said subset ones of said plurality of interrupts of a different one or more predetermined types, wherein the statistically indeterminate interrupt type of the received plurality of interrupts is determined from the masking step, thereby controlling on a per thread basis the processing of said plurality of interrupts according to the mask associated with a particular thread. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A system for operation in association with a digital signal processor for processing interrupts arising in a multithreaded processor, comprising:
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an interrupt register associated with said processor for receiving a plurality of interrupts each corresponding to an external interrupt of a statistically indeterminate interrupt type; thread control circuitry for associating a plurality of processing threads with said interrupt register, such that at least one of the plurality of processing threads is configured to receive at least one of said plurality of interrupts from said interrupt register; an event handling register for determining, for each of the plurality of processing threads, that the processing thread can take one of the plurality of interrupts if the processing thread has enabled interrupt processing and the processing thread is not an exception handler configured to handle internal exceptions; and a mask register for masking, based on the determiation, least a subset of said plurality of processing threads so as to receive within each of said threads within said subset only ones of said plurality of interrupts of one or more predetermined types and exclude from each of said threads within said subset ones of said plurality of interrupts of a different one or more predetermined types, wherein the statistically indeterminate interrupt type of the received plurality of interrupts is determined from the masking, thereby controlling on a per thread basis the processing of said plurality of interrupts according to the mask and the interrupt type. - View Dependent Claims (10, 11, 12, 13, 14, 15, 16)
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17. A digital signal processor for operation in support of a personal electronics device, said digital signal process comprising means for shared control processing means for processing a predetermined set of interrupt types in multi-threaded processing, said shared control processing means comprising:
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means for associating an interrupt controller with a plurality of processor pipeline threads; means for receiving a first external interrupt in said interrupt controller, said first external interrupt being of an arbitrary type; means for associating a first mask with said first external interrupt for enabling a set of said plurality of processor threads to accept said first external interrupt; means for directing said first external interrupt to a first available processor pipeline thread capable of accepting said first external interrupt and said first mask, the first available processor pipeline thread determined if the first available processor pipeline thread has enabled interrupt processing and the first available processor pipeline thread is not an exception handler configured to handle internal exceptions; means for receiving a second external interrupt in said interrupt controller, said second external interrupt being of an arbitrary type; means for associating a second mask with said second external interrupt for enabling a set of said plurality of processor pipeline threads to accept said second external interrupt; means for directing said second external interrupt to a next available processor pipeline thread capable of accepting said second external interrupt and said second mask, the next available processor pipeline thread determined if the next available processor pipeline thread has enabled interrupt processing and the second available processor pipeline thread is not an exception handler configured to handle internal exceptions; means for repeating said receiving steps, said associating steps, and said directing steps as external interrupts stream to said interrupt controller for processing by said digital signal processor, thereby providing to each of said set of said plurality of processor pipeline threads a flow of arbitrary external interrupts and associated masks in a distributed flow. - View Dependent Claims (18, 19, 20, 21, 22, 23, 24)
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25. A computer usable medium having computer readable program code means embodied therein for processing instructions on digital signal processor, the computer readable program code means comprising:
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computer readable program code means for receiving in an interrupt register a plurality of interrupts each corresponding to an external interrupt of a statistically indeterminate interrupt type; computer readable program code means for associating a plurality of processing threads with said interrupt register for receiving at least one of said plurality of interrupts from said interrupt register; computer readable program code means for determining, for each of the plurality of processing threads, that the processing thread can take one of the plurality of interrupts if the processing thread has enabled interrupt processing and the processing thread is not an exception handler configured to handle internal exceptions; and computer readable program code means for masking, based on the determination, at least a subset of said plurality of processing threads so as to receive within each of said threads within said subset only ones of said plurality of interrupts of one or more predetermined types and exclude from each of said threads within said subset ones of said plurality of interrupts of a different one or more predetermined types, wherein the statistically indeterminate interrupt type of the received plurality of interrupts is determined from the means for masking step, thereby controlling on a per thread basis the processing of said plurality of interrupts according to the mask associated with a particular thread. - View Dependent Claims (26)
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Specification