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Shared interrupt control method and system for a digital signal processor

  • US 7,702,889 B2
  • Filed: 10/18/2005
  • Issued: 04/20/2010
  • Est. Priority Date: 10/18/2005
  • Status: Active Grant
First Claim
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1. A method for processing interrupts arising in a multithreaded processor, comprising the steps of:

  • receiving in an interrupt register a plurality of interrupts, each of the plurality of interrupts corresponding to an external interrupt of a statistically indeterminate interrupt type;

    associating a plurality of processing threads with said interrupt register for receiving at least one of said plurality of interrupts from said interrupt register;

    determining, for each of the plurality of processing threads, that the processing thread can take one of the plurality of interrupts if the processing thread has enabled interrupt processing and the processing thread is not an exception handler configured to handle internal exceptions; and

    masking, based on the determining step, at least a subset of said plurality of processing threads so as to receive within each of said threads within said subset only ones of said plurality of interrupts of one or more predetermined types and exclude from each of said threads within said subset ones of said plurality of interrupts of a different one or more predetermined types,wherein the statistically indeterminate interrupt type of the received plurality of interrupts is determined from the masking step, thereby controlling on a per thread basis the processing of said plurality of interrupts according to the mask associated with a particular thread.

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