Decoy device in an integrated circuit

• US 7,702,926 B2
• Filed: 09/15/2004
• Issued: 04/20/2010
• Est. Priority Date: 07/15/1997
• Status: Expired due to Fees

• Current Assignee: Memjet Technology Ltd. (Memjet Limited)
• Original Assignee: Silverbrook Research Pty Limited
• Inventors: Silverbrook, Kia, Walmsley, Simon Robert
• Primary Examiner(s): Tran; Minh-Loan T
• Application Number:
  US10/940,653
• Publication Number:
  US 20050033705A1
• Time in Patent Office: 2,043 Days
• Field of Search: 713/194, 380/264
• US Class Current: 713/194
• CPC Class Codes: B41J 2/14 Structure thereof only for on-demand ink jet heads
• CPC Class Codes: B41J 2/16585 for paper-width or non-reciprocating print heads
• CPC Class Codes: B41J 2/17503 Ink cartridges
• CPC Class Codes: B41J 2/17513 Inner structure
• CPC Class Codes: B41J 2/17596 Ink pumps, ink valves
• CPC Class Codes: B42D 2035/34 Markings visible under particular conditions or containing coded information
• CPC Class Codes: B42D 25/00 Information-bearing cards or sheet-like structures characterised by identification or security features; Manufacture thereof printing processes to produce identification or security features B41M3/14
• CPC Class Codes: G06F 21/755 with measures against power attack
• CPC Class Codes: G06F 21/79 in semiconductor storage media, e.g. directly-addressable memories
• CPC Class Codes: G06F 21/86 Secure or tamper-resistant housings
• CPC Class Codes: G06F 2221/2129 Authenticate client device independently of the user
• CPC Class Codes: G06K 1/121 by printing code marks applying code marks to labels B65C9/46; marking or coding completed packages B65B61/26
• CPC Class Codes: G06K 19/06037 multi-dimensional coding
• CPC Class Codes: G06K 19/073 Special arrangements for circuits, e.g. for protecting identification code in memory protection against unauthorised use of computer memory G06F12/14
• CPC Class Codes: G06K 7/14 using light without selection of wavelength, e.g. sensing reflected white light G06K7/10831 - G06K7/1097 take precedence
• CPC Class Codes: G06K 7/1417 2D bar codes
• CPC Class Codes: G06Q 20/3674 involving authentication
• CPC Class Codes: G07F 7/08 by coded identity card or credit card or other personal identification means without personal verification means G07F7/02
• CPC Class Codes: G07F 7/086 by passive credit-cards adapted therefor, e.g. constructive particularities to avoid counterfeiting, e.g. by inclusion of a physical or chemical security-layer for security documents G07D7/00; for the reading of record-carriers in general G06K7/00; for the design of coded credit-cards G06K19/10
• CPC Class Codes: G07F 7/12 Card verification
• CPC Class Codes: G11C 11/56 : using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
• CPC Class Codes: H01L 23/576 : using active circuits
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 : Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H04L 2209/043 : of tables, e.g. lookup, substitution or mapping
• CPC Class Codes: H04L 2209/20 : Manipulating the length of blocks of bits, e.g. padding or block truncation
• CPC Class Codes: H04L 2209/60 : Digital content management, e.g. content distribution
• CPC Class Codes: H04L 2209/84 : Vehicles
• CPC Class Codes: H04L 9/0891 : Revocation or update of secret information, e.g. encryption key update or rekeying
• CPC Class Codes: H04L 9/0897 : involving additional devices, e.g. trusted platform module [TPM], smartcard or USB
• CPC Class Codes: H04L 9/3218 : using proof of knowledge, e.g. Fiat-Shamir, GQ, Schnorr, ornon-interactive zero-knowledge proofs
• CPC Class Codes: H04L 9/3273 : for mutual authentication network architectures or network communication protocols for achieving mutual authentication in a packet data network H04L63/0869
• CPC Class Codes: H04N 23/00 : Cameras or camera modules comprising electronic image sensors; Control thereof
• CPC Class Codes: H04N 5/2628 : Alteration of picture size, shape, position or orientation, e.g. zooming, rotation, rolling, perspective, translation

Abstract

An integrated circuit comprising:

• • at least one active device; and
  • at least one decoy device that emits light during a change in its state, wherein the operation of the at least one active device and the at least one decoy device is controlled so as to hinder optical detection of a pattern of the light emitted by the at least one active device.

Claims

1. An integrated circuit comprising:

at least one active device; and

at least one decoy device that emits light during a change in its state, wherein the operation of the at least one active device and the at least one decoy device is controlled so as to hinder optical detection of a pattern of the light emitted by the at least one active device.

2. An integrated circuit according to claim 1, wherein the at least one decoy device and the at least one active device are of similar type.

3. An integrated circuit according to claim 1, wherein the at least one decoy device has no functionality in the integrated circuit other than to hinder determination of the operation of at least part of the integrated circuit.

4. An integrated circuit according to claim 3, including a plurality of the active devices forming an active device circuit, and a plurality of the decoy devices forming a decoy circuit, wherein the decoy circuit is configured to operate on different data compared to the active device circuit.

5. An integrated circuit according to claim 3, including a plurality of the active devices forming an active device circuit and a plurality of the decoy devices forming a decoy circuit, wherein different clock signals are supplied to the active device circuit and the decoy circuit respectively.

6. An integrated circuit according to claim 5, including a clock circuit for generating a first clock signal, and a modification circuit for generating a second clock signal based on the first clock signal, wherein the first clock signal is supplied to one of the active device circuit and the decoy circuit, and the second clock signal is supplied to the other of the active device circuit and the decoy circuit.

7. An integrated circuit according to claim 6, wherein the modification circuit randomises or pseudo-randomises timing of the second clock signal with respect to the first clock signal.

8. An integrated circuit according to claim 1, wherein the at least one active device also emits light during a change in its state.

9. An integrated circuit according to claim 1, wherein the at least one active device emits less light than the at least one decoy device during their respective changes of state.

10. An integrated circuit according to claim 9, wherein the at least one decoy device and the at least one active device are of similar type.

11. An integrated circuit according to claim 9, wherein the at least one decoy device has no functionality in the integrated circuit other than to hinder determination of the operation of at least part of the integrated circuit.

12. An integrated circuit according to claim 11, including a plurality of the active devices forming an active device circuit, and a plurality of the decoy devices forming a decoy circuit, wherein the decoy circuit is configured to operate on different data compared to the active device circuit.

13. An integrated circuit according to claim 11, including a plurality of the active devices forming an active device circuit and a plurality of the decoy devices forming a decoy circuit, wherein different clock signals are supplied to the active device circuit and the decoy circuit respectively.

14. An integrated circuit according to claim 13, including a clock circuit for generating a first clock signal, and a modification circuit for generating a second clock signal based on the first clock signal, wherein the first clock signal is supplied to one of the active device circuit and the decoy circuit, and the second clock signal is supplied to the other of the active device circuit and the decoy circuit.

15. An integrated circuit according to claim 14, wherein the modification circuit randomises or pseudo-randomises timing of the second clock signal with respect to the first clock signal.

16. A method of hinder optical detection of a pattern of the light emitted by at least one active device in an integrated circuit, the method comprising the steps of:

(a) providing at least one at least one decoy device that emits light during a change in its state; and

(b) operating the decoy device such that it emits light during a change in its state, the size and timing of light emissions from the decoy device being selected so as to hinder optical detection of a pattern of the light emitted by the at least one active device.

17. A method according to claim 16, wherein step (b) includes supplying different clock signals to the active device circuit and the decoy circuit respectively.

18. A method according to claim 17, wherein the integrated circuit includes a clock circuit for generating a first clock signal, and a modification circuit for generating a second clock signal based on the first clock signal, the method comprising the steps of supplying the first clock signal either the at least one active device or the at least one decoy device, and supplying the second clock signal to the other of the at least one active device and the at least one decoy device.

19. A method according to claim 17, including the step, performed by the modification circuit, of randomising or pseudo-randomising timing of the second clock signal with respect to the first clock signal.