Method of fabricating super trench MOSFET including buried source electrode

• US 7,704,836 B2
• Filed: 03/31/2008
• Issued: 04/27/2010
• Est. Priority Date: 04/30/2004
• Status: Expired due to Fees

• Current Assignee: Siliconix Incorporated (Vishay Intertechnology Incorporated)
• Original Assignee: Siliconix Incorporated (Vishay Intertechnology Incorporated)
• Inventors: Shi, Sharon, Terrill, Kyle, Chen, Kuo-In, Lui, Kam Hong, Pattanayak, Deva N., Xu, Robert, Yue, Christiana, Bai, Yuming
• Primary Examiner(s): Garber; Charles D
• Assistant Examiner(s): Abdelaziez; Yasser A
• Application Number:
  US12/080,031
• Publication Number:
  US 20080182376A1
• Time in Patent Office: 757 Days
• Field of Search: 438/242, 438/248, 438/259, 438/391, 438/700, 257135-136, 257/242, 257/329
• US Class Current: 438/268
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41741 for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

In a trench MOSFET, the lower portion of the trench contains a buried source electrode, which is insulated from the epitaxial layer and semiconductor substrate but in electrical contact with the source region. When the MOSFET is in an “off” condition, the bias of the buried source electrode causes the “drift” region of the mesa to become depleted, enhancing the ability of the MOSFET to block current. The doping concentration of the drift region can therefore be increased, reducing the on-resistance of the MOSFET. The buried source electrode also reduces the gate-to-drain capacitance of the MOSFET, improving the ability of the MOSFET to operate at high frequencies. The substrate may advantageously include a plurality of annular trenches separated by annular mesas and a gate metal layer that extends outward from a central region in a plurality of gate metal legs separated by source metal regions.

Claims

1. A method of fabricating a MOSFET comprising:

forming a trench at a first surface of a semiconductor substrate, said substrate comprising dopant of a first conductivity type;

depositing a mask layer over said first surface, said mask layer lining the walls and floor of said trench;

removing a portion of said mask layer adjacent the floor of said trench, remaining portions of said mask layer remaining attached to sidewalls of said trench;

etching said substrate through said bottom of said trench with said remaining portions of said mask layer remaining attached to sidewalls of said trench so as to form a cavity in said substrate;

heating said substrate with said remaining portions of said mask layer remaining attached to sidewalls of said trench so as to form a first dielectric layer in said cavity;

removing said remaining portions of said mask layer;

introducing a first layer of a conductive material into said cavity, said first layer of conductive material being electrically isolated from said substrate by said first dielectric layer;

heating said substrate so as form a second dielectric layer at an exposed surface of said conductive material and a gate dielectric layer along walls of said trench;

introducing a second layer of conductive material into said trench;

forming a body region of a second conductivity type opposite to said first conductivity type in said substrate, said body region abutting said gate dielectric layer;

forming a source region of said first conductivity type abutting said gate oxide layer and forming a junction with said body region;

covering said second layer of conductive material in said trench with a third dielectric layer;

depositing a metal layer over said substrate, said metal layer being in electrical contact with said source region and

forming an electrical connection between said first layer of conductive material and said source region.

2. The method of claim 1 wherein forming said trench comprises etching said substrate.

3. The method of claim 1 wherein depositing said mask layer comprises depositing silicon nitride.

4. The method of claim 1 wherein removing a portion of said mask layer comprises using a reactive ion etch process.

5. The method of claim 1 wherein said first dielectric layer comprises silicon dioxide.

6. The method of claim 1 wherein introducing said first layer of conductive material into said cavity comprises depositing doped polysilicon.

7. The method of claim 1 wherein introducing said second layer of conductive material into said trench comprises depositing doped polysilicon.