Electro-optical apparatus, electronic apparatus, and method of manufacturing electro-optical apparatus

• US 7,704,859 B2
• Filed: 04/16/2007
• Issued: 04/27/2010
• Est. Priority Date: 05/23/2006
• Status: Active Grant

• Current Assignee: Japan Display West Incorporated (Japan Display Incorporated)
• Original Assignee: Epson Imaging Devices Corporation (Seiko Group)
• Inventors: Sato, Takashi
• Primary Examiner(s): Smith; Zandra
• Assistant Examiner(s): TYNES JR., LAWRENCE C
• Application Number:
  US11/785,217
• Publication Number:
  US 20070272982A1
• Time in Patent Office: 1,107 Days
• Field of Search: 257/347, 438/479
• US Class Current: 438/479
• CPC Class Codes: G02F 1/13454 Drivers integrated on the active matrix substrate G02F1/136277 takes precedence
• CPC Class Codes: H01L 27/1255 integrated with passive devices, e.g. auxiliary capacitors
• CPC Class Codes: H01L 29/4908 for thin film semiconductor, e.g. gate of TFT

Abstract

Provided is an electro-optical apparatus including a first thin-film transistor having a first gate electrode, a first gate insulating layer and a first active layer, which are respectively formed of a conductive film, an insulating film and a semiconductor film, in a pixel region of a device substrate, the apparatus including: a second thin-film transistor having a first gate electrode formed of the conductive film, a second gate insulating layer formed by removing a portion of the insulating film in a thickness direction and a second active layer formed of the semiconductor film, in a region other than the pixel region of the device substrate.

Claims

1. A method of manufacturing an electro-optical apparatus including a first thin-film transistor having a first gate electrode, a first gate insulating layer and a first active layer in a pixel region of a device substrate and a second thin-film transistor having a second gate electrode, a second gate insulating layer and a second active layer in a region other than the pixel region of the device substrate, the method comprising:

simultaneously forming the first gate electrode and the second gate electrode;

forming the first gate insulating layer and the second gate insulating layer;

forming the first active layer and the second active layer; and

thinning an insulating film which overlaps the second gate electrode at an upper layer side by etching to reduce the thickness of the second gate insulating layer to be smaller than that of the first gate insulating layer.

2. The method according to claim 1, wherein, in the forming of the gate insulating layer, the insulating film is formed in plural and is thinned while the insulating film is formed in plural, and

wherein the insulating film formed on the second gate electrode is removed by etching in the thinning of the insulating film.

3. The method according to claim 2, wherein, in the forming of the gate insulating layer, at least a final insulating film is formed at a vacuum atmosphere and the device substrate is continuously maintained in the vacuum atmosphere until the forming of the active layer starts, when the insulating film is formed in plural.

4. The method according to claim 1, wherein, in the forming of the gate electrode, a lower electrode of a storage capacitor is formed in the pixel region, and

wherein, in the thinning of the insulating film, the insulating film which overlaps the lower electrode at the upper layer side is etched to reduce the thickness of the dielectric layer of the storage capacitor to be smaller than that of the first gate insulating layer.

5. The method according to 1, wherein, in the forming of the gate electrode, a lower conductive layer is formed,

wherein, in the thinning of the insulating film, the insulting film which overlaps the lower conductive layer at the upper layer side is etched, and

wherein a contact hole for connecting the lower conductive layer which reaches the lower conductive layer is formed after the active layer is formed.