Fabrication of a micro-electromechanical system (MEMS) device from a complementary metal oxide semiconductor (CMOS)

• US 7,704,868 B2
• Filed: 04/11/2006
• Issued: 04/27/2010
• Est. Priority Date: 04/12/2005
• Status: Expired due to Fees

• Current Assignee: University of Florida Research Foundation, Incorporated (State University System of Florida)
• Original Assignee: University of Florida Research Foundation, Incorporated (State University System of Florida)
• Inventors: Ngo, Khai D. T., Xie, Huikai
• Primary Examiner(s): Landau; Matthew C
• Assistant Examiner(s): Sun; Yu-Hsi
• Application Number:
  US11/911,478
• Publication Number:
  US 20080169553A1
• Time in Patent Office: 1,477 Days
• Field of Search: 257/E21.627, 257/E21.641, 257/E23.067, 438/598, 438/637, 438/666, 438/667
• US Class Current: 438/598
• CPC Class Codes: H01L 27/0617 comprising components of the field-effect type H01L27/0251 takes precedence
• CPC Class Codes: H01L 27/08 including only semiconductor components of a single kind
• CPC Class Codes: H01L 28/10 Inductors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

Methods of fabricating micro-electromechanical system devices from complementary metal oxide semiconductors (CMOS) are provided.

Claims

1. A method of fabricating a micro-electromechanical system (MEMS) device from a complementary metal oxide semiconductor (CMOS) having a silicon layer and an oxide layer, the oxide layer being disposed on the silicon layer and having at least one metal layer disposed therein, the method comprising:

etching the silicon layer of the CMOS to form a trench through the silicon layer to expose a portion of the oxide layer;

depositing a silicon oxide layer on the silicon layer and exposed portion of the oxide layer within the trench;

etching the silicon oxide layer deposited on the exposed portion of the oxide layer to expose a portion of the metal disposed within the oxide layer;

electrodepositing a conductor within the trench, the conductor extending through the trench to the exposed portion of the metal;

etching the silicon layer of the CMOS to remove portions of the silicon layer adjacent the conductor;

depositing a silicon dioxide layer over the silicon layer and the conductor; and

etching portions of the oxide layer adjacent the conductor to form at least one trench adjacent the conductor defined by sidewalls of the silicon layer on which a layer of oxide remains deposited.

2. The method of claim 1, further comprising pre-treating the exposed portion of the metal prior to electrodepositing the conductor.

3. The method of claim 2, wherein pre-treating comprises treating the exposed portion of the metal to form an adhesion layer over the exposed portion of the metal.

4. The method of claim 1 further comprising planarizing the silicon layer after electroplating the conductor.

5. The method of claim 1, wherein etching the silicon layer of the CMOS to remove portions of the silicon layer adjacent the conductor comprises depositing a photoresist layer on portions of the silicon layer spaced apart from the conductor, etching exposed portions of the silicon layer adjacent the conductor, and removing the photoresist layer.

6. The method of claim 5, wherein depositing the photoresist layer on portions of the silicon layer spaced apart from the conductor comprises spinning a photosensitive material onto portions of the silicon layer, and wherein the photoresist layer is removed using an oxygen plasma applied after etching exposed portions of the silicon layer adjacent the conductor.

7. The method of claim 1, wherein etching the silicon layer of the CMOS to form a trench through the silicon layer to expose a portion of the oxide layer and etching the silicon layer of the CMOS to remove portions of the silicon layer adjacent the conductor each comprise a deep reactive ion etching.

8. The method of claim 1, wherein etching the silicon oxide layer deposited on the exposed portion of the oxide layer comprises an anisotropic dielectric etching.

13. The method of claim 1, further comprising:

electrodepositing a permalloy within the at least one trench adjacent the conductor.

14. The method of claim 13, further comprising:

etching the oxide layer to form a trench in a side of the oxide layer opposite the side in which the at least one trench adjacent the conductor is formed to form an opposing side trench.

15. The method of claim 14, further comprising:

electrodepositing in the opposing side trench a permalloy.

9. A method of fabricating a micro-electromechanical system (MEMS) device from a complementary metal oxide semiconductor (CMOS) having a silicon layer and an oxide layer, the oxide layer being disposed on the silicon layer and having a metal disposed therein, the method comprising:

etching the silicon layer of the CMOS to form a trench through the silicon layer to expose a portion of the oxide layer;

depositing a silicon oxide layer on the silicon layer and exposed portion of the oxide layer within the trench;

etching the silicon oxide layer deposited on the exposed portion of the oxide layer to expose a portion of the metal disposed within the oxide layer;

electrodepositing a conductor within the trench, the metal core extending through the trench to the exposed portion of the metal;

etching the silicon layer of the CMOS to remove portions of the silicon layer adjacent the conductor;

depositing a silicon dioxide layer over the silicon layer and the conductor;

etching portions of the oxide layer adjacent the conductor to form at least one trench adjacent the conductor defined by sidewalls of the silicon layer on which a layer of oxide remains deposited;

forming a dielectric layer over the silicon layer and the conductor;

electrodepositing a permalloy within the at least one trench adjacent the conductor;

etching the oxide layer to form a trench in a side of the oxide layer opposite the side in which the at least one trench adjacent the conductor is formed to form an opposing side trench; and

electrodepositing in the opposing side trench a permalloy.

10. The method of claim 9, wherein forming the dielectric layer comprises sputtering a dielectric layer at a predetermined angle relative to at least one of the silicon layer and conductor.

11. The method of claim 9, wherein electrodepositing a permalloy within the at least one trench adjacent the conductor comprises:

electrodepositing a metallic seed layer on exposed portions of the metal within the trench adjacent the conductor;

pre-treating the metallic seed layer; and

electrodepositing a permalloy on the pre-treated metallic seed layer.

12. The method of claim 11, wherein pre-treating comprises depositing an adhesion layer on the exposed portions of the metal within the trench adjacent the conductor.