Silicon carbide devices with hybrid well regions

• US 7,705,362 B2
• Filed: 08/31/2006
• Issued: 04/27/2010
• Est. Priority Date: 06/22/2004
• Status: Active Grant

• Current Assignee: CREE Incorporated (Wolfspeed, Inc.)
• Original Assignee: CREE Incorporated (Wolfspeed, Inc.)
• Inventors: Das, Mrinal Kanti, Ryu, Sei-Hyung
• Primary Examiner(s): Stark; Jarrett J
• Application Number:
  US11/513,473
• Publication Number:
  US 20060289874A1
• Time in Patent Office: 1,335 Days
• Field of Search: 257/77, 257/E21.054, 257/E29.104
• US Class Current: 257/77
• CPC Class Codes: H01L 29/0615 by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] LDD or drain offset regions H01L29/7833
• CPC Class Codes: H01L 29/0661 specially adapted for altering the breakdown voltage by removing semiconductor material at, or in the neighbourhood of, a reverse biased junction, e.g. by bevelling, moat etching, depletion etching
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/66068 the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
• CPC Class Codes: H01L 29/7395 Vertical transistors, e.g. vertical IGBT
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: Y10S 438/931 Silicon carbide semiconductor

Abstract

MOS channel devices and methods of fabricating such devices having a hybrid channel are provided. Exemplary devices include vertical power MOSFETs that include a hybrid well region of silicon carbide and methods of fabricating such devices are provided. The hybrid well region may include an implanted p-type silicon carbide well portion in a p-type silicon carbide epitaxial layer, an implanted p-type silicon carbide contact portion that contacts the implanted p-type silicon carbide well portion and extends to a surface of the p-type epitaxial layer and/or an epitaxial p-type silicon carbide portion, at least a portion of the epitaxial p-type silicon carbide well portion corresponding to a p-type channel region of the MOSFET.

Claims

1. A vertical silicon carbide MOSFET comprising:

a hybrid p-type silicon carbide well region on a silicon carbide substrate;

an n-type silicon carbide source region in the hybrid p-type silicon carbide well region;

an n-type silicon carbide channel region adjacent and spaced apart from the n-type silicon carbide source region, wherein a channel region of the MOSFET has both n-type and p-type portions;

a gate dielectric on the n-type silicon carbide channel region and at least a portion of the n-type silicon carbide source region;

a gate contact on the gate dielectric;

a first contact adjacent a portion of the hybrid p-type silicon carbide well region and the n-type silicon carbide source region; and

a second contact on the substrate,

wherein the hybrid p-type silicon carbide well region comprises;

an implanted p-type silicon carbide well portion in a p-type silicon carbide epitaxial layer; and

an implanted p-type silicon carbide contact portion that contacts the implanted p-type silicon carbide well portion and extends into the p-type epitaxial layer.

2. The vertical silicon carbide MOSFET of claim 1, wherein the hybrid p-type silicon carbide well region further comprises:

an epitaxial p-type silicon carbide portion of the p-type silicon carbide epitaxial layer, at least a portion of which corresponds to the p-type portion of the channel region of the MOSFET.

3. The vertical silicon carbide MOSFET of claim 1, further comprising an n-type epitaxial layer between the hybrid p-type silicon carbide well region and the substrate.

4. The vertical silicon carbide MOSFET of claim 2, wherein the n-type source region and the n-type channel region comprise regions of the p-type epitaxial layer with implanted n-type dopants.

5. The vertical silicon carbide MOSFET of claim 1, further comprising a voltage absorbing region around the silicon carbide device MOSFET.

6. The vertical silicon carbide MOSFET of claim 2 further comprising a passivating layer on exposed portions of the p-type epitaxial layer.

23. The vertical silicon carbide MOSFET of claim 2, wherein the implanted p-type silicon carbide contact portion has a carrier concentration greater than a carrier concentration of the implanted p-type silicon carbide well portion.

24. The vertical silicon carbide MOSFET of claim 23, wherein the implanted p-type silicon carbide well portion has a carrier concentration of from about 1.0×

10¹⁷ cm<sup>−

3</sup> to about 1×

10¹⁸ cm<sup>−

3</sup> and wherein the implanted p-type silicon carbide contact portion has a carrier concentration of about 1.0×

10¹⁹ cm<sup>−

3</sup>.

7. A unit cell of a vertical silicon carbide power device, comprising:

a first p-type silicon carbide epitaxial layer on an n-type silicon carbide drift region on an n-type silicon carbide substrate;

at least one first region of n-type silicon carbide which extends through the first p-type silicon carbide epitaxial layer to the n-type drift region;

at least one second region of n-type silicon carbide which is adjacent and spaced apart from the first region of n-type silicon carbide;

at least one implanted buried region of p-type silicon carbide in the first p-type silicon carbide epitaxial layer, the at least one implanted buried region having a higher carrier concentration than the p-type silicon carbide epitaxial layer and being positioned between the at least one second region of n-type silicon carbide and the drift region and being substantially aligned with a side of the at least one second region of n-type silicon carbide adjacent the at least one first region of n-type silicon carbide; and

a gate dielectric over the first region of n-type silicon carbide in the first p-type silicon carbide layer and at least a portion of the second region of n-type silicon carbide.

8. The unit cell of claim 7, further comprising:

at least one contact region of p-type silicon carbide that extends through the at least one second region of n-type silicon carbide to the at least one buried region of p-type silicon carbide.

9. The unit cell of claim 8, further comprising:

a gate contact on the gate dielectric;

a first contact so as to contact a portion of the at least one contact region and the second region of n-type silicon carbide; and

a second contact on the substrate.

10. The unit cell of claim 7, further comprising an n-type epitaxial layer between the first p-type silicon carbide epitaxial layer and the substrate.

11. The unit cell of claim 7, wherein the first and second regions of n-type silicon carbide are regions of the first p-type epitaxial layer with implanted n-type dopants.

12. The unit cell of claim 7 further comprising a passivating layer on exposed portions of the first p-type epitaxial layer.

13. The unit cell of claim 7, further comprising a voltage absorbing region around the silicon carbide device.

14. A silicon carbide Metal-Oxide Semiconductor (MOS) gated device, comprising:

a hybrid silicon carbide well region of a first conductivity type, comprising;

a first silicon carbide epitaxial layer of the first conductivity type;

an implanted well portion of the first conductivity type in the silicon carbide epitaxial layer; and

an implanted contact portion that contacts the implanted well portion and extends to a surface of the epitaxial layer;

a first silicon carbide region of a second conductivity type at least in part within the hybrid silicon carbide well region;

a second silicon carbide region of the second conductivity type adjacent the well region and spaced apart from the first silicon carbide region;

a gate dielectric on the second silicon carbide region and at least a portion of the first silicon carbide region;

a gate contact on the gate dielectric; and

wherein an unimplanted portion of the epitaxial layer corresponds to a channel region of the device.

15. The device of claim 14, wherein the first conductivity type is p-type and the second conductivity type is n-type.

16. The device of claim 14, wherein the first conductivity type is n-type and the second conductivity type is p-type.

17. The device of claim 14, wherein the epitaxial layer comprises an epitaxial layer on a drift region of the second conductivity type, wherein the first region of silicon carbide extends to the drift region and wherein the device comprises a field effect transistor.

18. The device of claim 17, wherein the drift region comprises an epitaxial layer of silicon carbide.

19. The device of claim 17, wherein the drift region comprises a silicon carbide substrate.

20. The device of claim 14, wherein the epitaxial layer comprises an epitaxial layer on a layer of first conductivity type silicon carbide, wherein the first region of silicon carbide extends to the layer of first conductivity type silicon carbide and wherein the device comprises an insulated gate bipolar transistor.

21. The device of claim 20, wherein the layer of first conductivity silicon carbide comprises an epitaxial layer of silicon carbide.

22. The device of claim 20, wherein the layer of first conductivity type silicon carbide comprises a silicon carbide substrate.

25. A vertical silicon carbide MOSFET comprising:

a hybrid p-type silicon carbide well region on a silicon carbide substrate, wherein the hybrid p-type silicon carbide well region comprises;

an implanted p-type silicon carbide well portion in a p-type silicon carbide epitaxial layer; and

an implanted p-type silicon carbide contact portion that contacts the implanted p-type silicon carbide well portion and extends into the p-type epitaxial layer, the implanted p-type silicon carbide contact portion having a carrier concentration greater than a carrier concentration of the implanted p-type silicon carbide well portion;

an n-type silicon carbide source region in the hybrid p-type silicon carbide well region;

an implanted n-type silicon carbide channel region adjacent and spaced apart from the n-type silicon carbide source region;

a gate dielectric on the implanted n-type silicon carbide channel region;

a gate contact on the gate dielectric;

a first contact adjacent a portion of the hybrid p-type silicon carbide well region and the n-type silicon carbide source region; and

a second contact on the substrate.

26. A silicon carbide Metal-Oxide Semiconductor (MOS) gated device, comprising:

a hybrid silicon carbide well region of a first conductivity type, including;

a first silicon carbide epitaxial layer of the first conductivity type;

an implanted well portion of the first conductivity type in the silicon carbide epitaxial layer; and

an implanted contact portion having the first conductivity type that contacts the implanted well portion,

wherein an unimplanted portion of the epitaxial layer corresponds to a channel region of the device.

27. The silicon carbide MOS gated device of claim 26, wherein the implanted contact portion has a carrier concentration greater than a carrier concentration of the implanted well portion.