Insulated gate type thyristor

• US 7,705,368 B2
• Filed: 02/15/2007
• Issued: 04/27/2010
• Est. Priority Date: 03/24/2006
• Status: Active Grant

• Current Assignee: Pakal Technologies, Inc.
• Original Assignee: Fujifilm Corporation (Fujifilm Holdings Corporation)
• Inventors: Rodov, Vladimir, Akiyama, Hidenori
• Primary Examiner(s): Ngo; Ngan
• Assistant Examiner(s): LIU, BENJAMIN T
• Application Number:
  US11/706,184
• Publication Number:
  US 20070235752A1
• Time in Patent Office: 1,167 Days
• Field of Search: 257/137, 257/138, 257/147, 257/153, 257/175, 257/176, 257/E29.036, 257/E29.037, 257/E29.038, 257/E29.046, 257/E29.047, 257/E29.048, 257/E29.115, 257/E29.125, 257/E29.211, 257/E29.214
• US Class Current: 257/153
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/42308 Gate electrodes for thyristors
• CPC Class Codes: H01L 29/7455 produced by an insulated gate structure
• CPC Class Codes: H01L 29/749 with turn-on by field effect

Abstract

An insulated gate type thyristor includes: a first current terminal semiconductor region of a first conductivity type having a high impurity concentration; a first base semiconductor region of a second conductivity type opposite to the first conductivity type having a low impurity concentration and formed on the first current terminal semiconductor region; a second base semiconductor region of the first conductivity type having a low impurity concentration and formed on the first base semiconductor region; a second current terminal semiconductor region of the second conductivity type having a high impurity concentration and formed on the second base semiconductor region; a trench passing through the second current terminal semiconductor region and entering the second base semiconductor region leaving some depth thereof, along a direction from a surface of the second current terminal semiconductor region toward the first base semiconductor region; and an insulated gate electrode structure formed in the trench.

Claims

1. An insulated gate type three terminal thyristor comprising:

a first current terminal semiconductor region of a first conductivity type having a first impurity concentration;

a first base semiconductor region of a second conductivity type opposite to the first conductivity type having a second impurity concentration and formed on said first current terminal semiconductor region;

a second base semiconductor region of the first conductivity type having a third impurity concentration lower than the first impurity concentration and formed on said first base semiconductor region;

a second current terminal semiconductor region of the second conductivity type having a fourth impurity concentration higher than the second impurity concentration and formed on said second base semiconductor region;

a trench structure passing through said second current terminal semiconductor region and entering said second base semiconductor region without reaching the first base semiconductor region;

a first electrode connected to the first current terminal semiconductor region;

a second electrode connected to the second current terminal semiconductor region; and

a third electrode having an insulated gate electrode structure formed in said trench structure,

wherein said trench structure divides an upper portion of said second base semiconductor region into a plurality of regions, and is formed surrounding each divided region,

wherein said first base, second base, first current terminal and second current terminal semiconductor regions are made of silicon,

wherein the divided upper portions of said second base semiconductor region have stripe-shaped portions as viewed in plan, and

wherein said trench structure surrounding said stripe-shaped portion defines a common contact recess at one end along a stripe longitudinal direction, and said insulating gate electrode structure includes a gate electrode portion surrounding said stripe-shaped portion in the upper position of said second base semiconductor region and a contact portion formed in said common contact recess.

2. The insulated gate type three terminal thyristor according to claim 1, further comprising:

an insulating layer formed covering said insulated gate electrode structure and said second current terminal semiconductor region;

current terminal electrodes passing through said insulating layer and contacting said stripe-shaped portions at a plurality of positions; and

a gate lead electrode passing through said insulating layer and contacting said contact portion of said insulated gate electrode structure.

3. The insulated gate type three terminal thyristor according to claim 1, wherein the upper portion of said second base semiconductor region surrounded by said trench structure has a stripe width L and a Debye length L_D where a relation of 50*L_D≧

L is satisfied.

4. The insulated gate type three terminal thyristor according to claim 1, wherein said insulated gate electrode structure includes a silicon oxide film formed on a surface of said trench structure, a polysilicon film deposited on the silicon oxide film and a silicide film deposited on the polysilicon film.

5. The insulated gate type three terminal thyristor according to claim 1, wherein said trench structure is formed digging one thirds or more of a thickness of said second base semiconductor region.

6. The insulated gate type three terminal thyristor according to claim 1, wherein the first conductivity type is a p-type and the second conductivity type is an n-type.

7. The insulated gate type three terminal thyristor according to claim 6, wherein said first current terminal semiconductor region is a high impurity concentration p-type silicon substrate, said first base semiconductor region is a low impurity concentration n-type silicon epitaxial layer, said second base semiconductor region is a p-type region formed in a surface layer of said epitaxial layer through ion implantation, and said second current terminal semiconductor region is a high impurity concentration n-type region formed in an upper portion of said p-type region through ion implantation.

8. The insulated gate type three terminal thyristor according to claim 1, wherein said second base semiconductor region is a well region formed in said first base semiconductor region, and the insulated gate type thyristor further comprising a guard ring of the first conductivity type formed in said first base semiconductor region and surrounding said well region.

9. The insulated gate type three terminal thyristor according to claim 1, wherein a plurality of trench structures are formed and said insulated gate electrode structure is formed in each trench structure.

10. The insulated gate type three terminal thyristor according to claim 1, wherein said first base semiconductor region and said second base semiconductor region are electrically floating.

11. The insulated gate type three terminal thyristor according to claim 1, wherein said second current terminal semiconductor region is formed directly on said second base semiconductor region.