Semiconductor die with an integrated inductor

• US 7,705,421 B1
• Filed: 11/18/2005
• Issued: 04/27/2010
• Est. Priority Date: 11/18/2005
• Status: Active Grant

• Current Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Original Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Inventors: Yegnashankaran, Visvamohan
• Primary Examiner(s): Gurley; Lynne A
• Assistant Examiner(s): ARENA, ANDREW OWENS
• Application Number:
  US11/283,296
• Time in Patent Office: 1,621 Days
• Field of Search: 257/531, 257/E21.022
• US Class Current: 257/531
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 27/016 Thin-film circuits
• CPC Class Codes: H01L 28/10 Inductors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/3011 Impedance

Abstract

An integrated circuit inductor has a number of vertical metal segments, a number of lower metal straps that electrically connect alternate metal segments, and a number of upper metal straps that electrically connect alternate metal segments to form a continuous electrical path. Layers of a ferromagnetic material are formed normal to the metal segments to extend past at least two sides of each metal segment to increase the inductance of the inductor.

Claims

1. A semiconductor die comprising:

a substrate having a top surface; and

a metal interconnect structure that contacts the top surface of the substrate, the metal interconnect structure having;

a dielectric material;

a number of metal segments that touch the dielectric material, each metal segment having a lower end and an upper end, the number of metal segments being spaced apart and including a first metal segment, a second metal segment, and a third metal segment, the first, second, and third metal segments each having a first side region, a second side region opposite the first side region, a third side region, and a fourth side region opposite the third side region;

a number of lower metal straps, each lower metal strap electrically connecting together the lower end of a metal segment and the lower end of an adjacent metal segment, a lower metal strap directly touching the lower end of the first metal segment and the lower end of the second metal segment;

a number of upper metal straps, each upper metal strap electrically connecting together the upper end of a metal segment and the upper end of an adjacent metal segment, an upper metal strap directly touching the upper end of the second metal segment and the upper end of the third metal segment,

a continuous electrical path extending from a first end to a second end through each metal segment, each lower metal strap, and each upper metal strap; and

a trace that touches the dielectric material and lies substantially only parallel to the top surface of the substrate, the trace including a magnetic material, having a plurality of turns that wind between the number of metal segments, and enclosing three of the four side regions of each of the first, second, and third metal segments.

2. The semiconductor die of claim 1 wherein:

each lower metal strap contacts only two metal segments; and

each upper metal strap contacts only two metal segments.

3. The semiconductor die of claim 1 wherein one of the three side regions of the first metal segment enclosed by the trace and one of the three side regions of the second metal segment enclosed by the trace are different.

4. The semiconductor die of claim 1 wherein the trace is a ferromagnetic material.

5. The semiconductor die of claim 1 wherein each metal segment includes metal regions and vias, each via directly touching a vertically adjacent pair of metal regions.

6. The semiconductor die of claim 1 wherein the trace forms a continuous loop.

7. The semiconductor die of claim 1 wherein the continuous electrical path extends around a periphery of the die.

8. A semiconductor die comprising:

a substrate having a top surface; and

a metal interconnect structure that contacts the top surface of the substrate, the metal interconnect structure having;

a dielectric material;

a number of metal segments that touch the dielectric material, each metal segment having a lower end and an upper end, the number of metal segments being spaced apart and including a first metal segment, a second metal segment, and a third metal segment, the first, second, and third metal segments each having a first side region, a second side region opposite the first side region, a third side region, and a fourth side region opposite the third side region;

a number of lower metal straps, each lower metal strap electrically connecting together the lower end of a metal segment and the lower end of an adjacent metal segment, a lower metal strap directly touching the lower end of the first metal segment and the lower end of the second metal segment;

a number of upper metal straps, each upper metal strap electrically connecting together the upper end of a metal segment and the upper end of an adjacent metal segment, an upper metal strap directly touching the upper end of the second metal segment and the upper end of the third metal segment,

a continuous electrical path extending from a first end to a second end through each metal segment, each lower metal strap, and each upper metal strap; and

a trace that touches the dielectric material and lies substantially parallel to the top surface of the substrate, the trace including a magnetic material, having a plurality of turns that wind between the number of metal segments, and enclosing only three of the four side regions of each of the first, second, and third metal segments.

9. The semiconductor die of claim 8 wherein the trace forms a continuous loop.

10. The semiconductor die of claim 8 wherein the trace is a ferromagnetic material.

11. The semiconductor die of claim 8 wherein one of the three side regions of the first metal segment enclosed by the trace and one of the three side regions of the second metal segment enclosed by the trace are different.

12. The semiconductor die of claim 8 wherein:

each lower metal strap contacts only two metal segments; and

each upper metal strap contacts only two metal segments.

13. The semiconductor die of claim 8 wherein each metal segment includes metal regions and vias, each via directly touching a vertically adjacent pair of metal regions.

14. The semiconductor die of claim 8 wherein the continuous electrical path extends around a periphery of the die.

15. A semiconductor die comprising:

a substrate having a top surface; and

a metal interconnect structure that contacts the top surface of the substrate, the metal interconnect structure having;

a dielectric material;

a number of metal segments that touch the dielectric material, each metal segment having a lower end and an upper end, the number of metal segments being spaced apart and including a first metal segment, a second metal segment, and a third metal segment, the first, second, and third metal segments each having a first side region, a second side region opposite the first side region, a third side region, and a fourth side region opposite the third side region;

a number of lower metal straps, each lower metal strap electrically connecting together the lower end of a metal segment and the lower end of an adjacent metal segment, a lower metal strap directly touching the lower end of the first metal segment and the lower end of the second metal segment;

a number of upper metal straps, each upper metal strap electrically connecting together the upper end of a metal segment and the upper end of an adjacent metal segment, an upper metal strap directly touching the upper end of the second metal segment and the upper end of the third metal segment,

a continuous electrical path extending from a first end to a second end through each metal segment, each lower metal strap, and each upper metal strap; and

two or more traces that each touch the dielectric material and lie substantially only parallel to the top surface of the substrate, each trace being electrically isolated from each other trace, including a magnetic material, having a plurality of turns that wind between the number of metal segments, and enclosing three of the four side regions of each of the first, second, and third metal segments.

16. The semiconductor die of claim 15 wherein each trace forms a continuous loop.

17. The semiconductor die of claim 15 wherein each trace is a ferromagnetic material.

18. The semiconductor die of claim 15 wherein:

each lower metal strap contacts only two metal segments; and

each upper metal strap contacts only two metal segments.

19. The semiconductor die of claim 15 wherein the continuous electrical path extends around a periphery of the die.

20. The semiconductor die of claim 15 wherein one of the three side regions of the first metal segment enclosed by the trace and one of the three side regions of the second metal segment enclosed by the trace are different.