Integration of a SiGe- or SiGeC-based HBT with a SiGe- or SiGeC-strapped semiconductor device

• US 7,705,426 B2
• Filed: 11/10/2006
• Issued: 04/27/2010
• Est. Priority Date: 11/10/2006
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Voldman, Steven
• Primary Examiner(s): Vu; David
• Assistant Examiner(s): Taylor; Earl N
• Application Number:
  US11/558,480
• Publication Number:
  US 20080111154A1
• Time in Patent Office: 1,264 Days
• Field of Search: 257/51, 257/197, 257/592, 257/E29.045, 257/E29.188
• US Class Current: 257/592
• CPC Class Codes: H01L 21/8249 Bipolar and MOS technology
• CPC Class Codes: H01L 27/0635 in combination with bipolar transistors and diodes, or resistors, or capacitors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H10B 10/00 Static random access memory [SRAM] devices
• CPC Class Codes: H10B 12/09 with simultaneous manufacture of the peripheral circuit region and memory cells

Abstract

The present invention provides an integrated semiconductor device that includes a semiconductor substrate, a first device containing a heterojunction bipolar transistor (HBT) located in a first region of the semiconductor substrate, wherein the HBT includes a base region containing a first portion of a SiGe or SiGeC layer, and a second device located in a second region of the semiconductor substrate, wherein the second device includes an interconnect containing a second portion of the SiGe or SiGeC layer. In a specific embodiment of the present invention, the second device is a memory device including a trench capacitor and a field effect transistor (FET) that are electrically connected together by the second portion of the SiGe or SiGeC layer. Alternatively, the second device is a trench-biased PNPN silicon controlled rectifier (SCR). The present invention also provides a novel reversibly programmable device or a novel memory device formed by a novel trench-biased SCR device.

Claims

1. An integrated semiconductor device comprising:

a semiconductor substrate;

a first semiconductor device comprising a heterojunction bipolar transistor (HBT) located in a first region of the semiconductor substrate, wherein said HBT comprises a base region containing a first portion of a SiGe or SiGeC layer; and

a second semiconductor device located in a second region of the semiconductor substrate, wherein said second semiconductor device comprises an interconnect containing a second portion of the SiGe or SiGeC layer; and

wherein the second portion of the SiGe or SiGeC layer is coplanar with an upper surface of the semiconductor substrate.

2. The integrated semiconductor device of claim 1, wherein the second portion of the SiGe or SiGeC layer comprises a polycrystalline section and a single crystal section.

3. The integrated semiconductor device of claim 1, wherein said second semiconductor device comprises a memory device including a trench capacitor and a field effect transistor (FET) that are electrically connected together by the second portion of the SiGe or SiGeC layer.

4. The integrated semiconductor device of claim 1, wherein the semiconductor substrate is doped with a p-type dopant species, wherein said second semiconductor device comprises a trench-biased PNPN silicon controlled rectifier, which includes a p-type anode that is located over an n-well in the semiconductor substrate, an n-type cathode that is located over the semiconductor substrate and is spaced apart from the n-well, and a polysilicon-filled trench that is located in the semiconductor substrate abutting the n-well region, and wherein the second portion of the SiGe or SiGeC layer is located over and electrically contacts the polysilicon-filled trench for applying a bias voltage to said trench.

5. The integrated semiconductor device of claim 4, wherein the polysilicon-filled trench encircles the n-well.

6. The integrated semiconductor device of claim 4, wherein the polysilicon-filled trench is located at one side of the n-well between the n-well and the n-cathode.

7. The integrated semiconductor device of claim 4, wherein the trench-biased PNPN silicon controlled rectifier comprises five electrodes, which include the p-type anode, the n-type cathode, a first additional electrode electrically connected with the n-well, a second additional electrode electrically connected with the p-doped semiconductor substrate, and a third additional electrode electrically connected with the second portion of the SiGe or SiGeC layer.

8. The integrated semiconductor device of claim 4, wherein the second portion of the SiGe or SiGeC layer extends to form further electrical contact with the p-doped semiconductor substrate, and wherein the trench-biased PNPN silicon controlled rectifier comprises four electrodes, which include the p-type anode, the n-type cathode, a first additional electrode electrically connected with the n-well, and a second additional electrode electrically connected with the second portion of the SiGe or SiGeC layer.

9. The integrated semiconductor device of claim 4, wherein the second portion of the SiGe or SiGeC layer extends to further form electrical contact with the n-well, and wherein the trench-biased PNPN silicon controlled rectifier comprises four electrodes, which include the p-type anode, the n-type cathode, a first additional electrode electrically connected with the p-doped semiconductor substrate, and a second additional electrode electrically connected with the second portion of the SiGe or SiGeC layer.

10. A method for forming an integrated semiconductor device comprising:

providing a semiconductor substrate;

forming a first semiconductor device comprising a heterojunction bipolar transistor (HBT) in a first region of the semiconductor substrate and a second semiconductor device in a second region of the semiconductor substrate;

forming a SiGe or SiGeC layer over the first and second regions, wherein a first portion of the SiGe or SiGeC layer forms a base region in the HBT, and wherein a second portion of the SiGe or SiGeC layer forms an interconnect in said second semiconductor device; and

wherein the second portion of the SiGe or SiGeC layer is coplanar with an upper surface of the semiconductor substrate.

11. The method of claim 10, wherein the second semiconductor device comprises a memory device including a trench capacitor and a field effect transistor (FET) that are electrically connected together by the second portion of the SiGe or SiGeC layer.

12. The method of claim 10, wherein the second semiconductor device comprises a trench-biased PNPN silicon controlled rectifier, which includes a p-type anode that is located over an n-well in the semiconductor substrate, an n-type cathode that is located over the semiconductor substrate and is spaced apart from the n-well, and a polysilicon-filled trench that is located in the semiconductor substrate abutting the n-well region, and wherein the second portion of the SiGe or SiGeC layer is located over and electrically contacts the polysilicon-filled trench for applying a bias voltage to said trench.