Three dimensional multi layer memory and control logic integrated circuit structure

• US 7,705,466 B2
• Filed: 09/26/2003
• Issued: 04/27/2010
• Est. Priority Date: 04/04/1997
• Status: Expired due to Fees

• Current Assignee: Elm 3DS Innovations LLC
• Original Assignee: ELM TECHNOLOGY CORPORATION
• Inventors: Leedy, Glenn J
• Primary Examiner(s): Dickey; Thomas L
• Application Number:
  US10/672,961
• Publication Number:
  US 20040070063A1
• Time in Patent Office: 2,405 Days
• Field of Search: 257/777, 257/778, 257/685, 257/686, 365/200, 365/201, 365/230.06, 365/230.6, 438/455, 438/459, 438/977, 438/107, 438/108
• US Class Current: 257/777
• CPC Class Codes: G11C 5/02 Disposition of storage elements, e.g. in the form of a matrix array
• CPC Class Codes: G11C 5/06 Arrangements for interconnecting storage elements electrically, e.g. by wiring
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2224/8083 Solid-solid interdiffusion
• CPC Class Codes: H01L 2224/8384 Sintering
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 29/02 Semiconductor bodies ; Multistep manufacturing processes therefor
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H10B 12/50 Peripheral circuit region structures
• CPC Class Codes: Y10S 438/977 Thinning or removal of substrate

Abstract

A Three-Dimensional Structure (3DS) Memory allows for physical separation of the memory circuits and the control logic circuit onto different layers such that each layer may be separately optimized. One control logic circuit suffices for several memory circuits, reducing cost. Fabrication of 3DS memory involves thinning of the memory circuit to less than 50 μm in thickness and bonding the circuit to a circuit stack while still in wafer substrate form. Fine-grain high density inter-layer vertical bus connections are used. The 3DS memory manufacturing method enables several performance and physical size efficiencies, and is implemented with established semiconductor processing techniques.

Claims

1. An integrated circuit structure comprising:

a first substrate comprising a first surface having interconnect contacts; and

a second substrate having a thickness of about 50 microns or less and comprising a first surface and a second surface at least one of which has interconnect contacts, wherein the second surface is opposite the first surface and wherein the second surface of the second substrate is polished; and

conductive paths between the interconnect contacts of the first surface of the first substrate and said one of the first surface of the second substrate and the second surface of the second substrate;

wherein the first surface of the first substrate and one of the first surface of the second substrate and the second surface of the second substrate are bonded in a stacked relationship, the first substrate overlapping at least a majority of the second substrate.

2. The integrated circuit structure of claim 1, wherein the second substrate is one of a thin monocrystalline semiconductor substrate and a thin polycrystalline semiconductor substrate.

3. The integrated circuit structure of claim 1, wherein circuitry is formed on the second substrate, said circuitry comprising one of active circuitry and passive circuitry.

4. The integrated circuit structure of claim 1, wherein circuitry is formed on the second substrate comprising both active circuitry and passive circuitry.

5. The integrated circuit structure of claim 1, wherein the first substrate is a substrate having circuitry formed thereon.

6. The integrated circuit structure of claim 5, wherein the circuitry of the first substrate comprises one of active circuitry and passive circuitry.

7. The integrated circuit structure of claim 5, wherein the circuitry of the first substrate comprises both active circuitry and passive circuitry.

8. The integrated circuit structure of claim 1, further comprising:

at least one additional thin substrate having circuitry formed thereon;

a first of said at least one additional thin substrate being bonded to the second substrate and any additional thin substrates being bonded to a directly adjacent additional thin substrate; and

conductive paths formed between said first of said at least one additional thin substrate and at least one of said first and second substrates and also between each additional thin substrate and at least one of said substrates of the integrated circuit structure.

9. The integrated circuit structure of claim 8, wherein at least two of the first, the second and the at least one additional thin substrates are formed using different respective process technologies, wherein the different respective process technologies are selected from the group consisting of a DRAM process technology, a SRAM process technology, a FLASH process technology, an EPROM process technology, an EEPROM process technology, a Ferroelectric process technology and a Giant Magneto Resistance process technology.

10. The integrated circuit structure of claim 8, wherein at least one of the first, the second and the at least one additional thin substrates comprises a microprocessor.

11. The integrated circuit structure of claim 8, wherein:

at least one substrate of the first, the second and the at least one additional thin substrates has memory circuitry formed thereon; and

at least one substrate of the first, the second and the at least one additional thin substrates has logic circuitry formed thereon that performs tests on the at least one substrate that has memory circuitry formed thereon.

12. The integrated circuit structure of claim 8, wherein at least one substrate of the first, the second and the at least one additional thin substrates has memory circuitry formed thereon, the memory circuitry having a plurality of memory locations, wherein at least one memory location of the plurality of memory locations is used for sparing and wherein data from the at least one memory location on the at least one substrate having memory circuitry formed thereon is used instead of data from a defective memory location on the at least one substrate that has memory circuitry formed thereon.

13. The integrated circuit structure of claim 8, wherein:

at least one substrate of the first, the second and the at least one additional thin substrates has memory circuitry formed thereon; and

at least one substrate of the first, the second and the at least one additional thin substrates has logic circuitry formed thereon that performs programmable gate line address assignment with respect to the at least one substrate having memory circuitry formed thereon.

14. The integrated circuit structure of claim 8, further comprising a plurality of interior vertical interconnections that traverse at least one of the first, the second and the at least one additional thin substrates.

15. The integrated circuit structure of claim 8, wherein circuitry is formed on at least two of the first, the second and the at least one additional thin substrates, and wherein information processing is performed on data routed between the circuitry of at least two of the first, the second and the at least one additional thin substrates.

16. The integrated circuit structure of claim 8, wherein at least one of the first, the second and the at least one additional thin substrates comprises reconfiguration circuitry.

17. The integrated circuit structure of claim 8, wherein at least one of the first, the second, and the at least one additional thin substrates has logic circuitry formed thereon for performing at least one function from the group consisting of:

virtual memory management, ECC, indirect addressing, content addressing, data compression, data decompression, graphics acceleration, audio encoding, audio decoding, video encoding, video decoding, voice recognition, handwriting recognition, power management and database processing.

18. The integrated circuit structure of claim 8, further comprising:

a memory array having a plurality of memory storage cells, a plurality of data lines, and a plurality of gate lines, wherein each memory storage cell stores a data value and has circuitry for coupling the data value to one of the plurality of data lines in response to receiving a gate control signal from one of the plurality of gate lines;

circuitry that generates the gate control signal in response to receiving an address, including means for mapping addresses to gate lines; and

a controller that determines if at least one of the plurality of memory cells is defective and alters said mapping to remove references to the one of the plurality of memory cells that is defective.

19. The integrated circuit structure of claim 8, further comprising:

at least one controller substrate having logic circuitry formed thereon;

at least one memory substrate having memory circuitry formed thereon;

a plurality of data lines and a plurality of gate lines on each memory substrate;

an array of memory cells on each memory substrate, wherein each memory cell stores a data value and has circuitry that couples the data value to one of the plurality of data lines in response to selecting one of the plurality of gate lines;

a gate line selection circuit that enables a gate line for a memory operation, wherein the gate line selection circuit comprises programmable gates for receiving address assignments for at least one gate line of the plurality of gate lines and wherein the address assignments are for determining which of the plurality of gate lines is selected for each address assignment; and

controller substrate logic that determines if at least one memory cell of the array of memory cells is defective and alters the address assignments of the plurality of gate lines to remove references to the gate line that causes the defective memory cell to couple a data value to one of the plurality of data lines.

20. The integrated circuit structure of claim 19, wherein the controller substrate logic is configured to:

test the array of memory cells periodically to determine if at least one of the array of memory cells is defective; and

remove references in the address assignments to gate lines that cause detected defective memory cells to couple data values to the plurality of data lines.

21. The integrated circuit structure of claim 19, further comprising:

programmable logic to prevent the use of data values from the plurality of data lines when gate lines cause detected defective memory cells to couple data values to the plurality of data lines.

22. The integrated circuit structure of claim 19, wherein the array of memory cells are arranged within physical space in a physical order and are arranged within an address space in a logical order and wherein the physical order of at least one memory cell is different than the logical order of the at least one memory cell.

23. The integrated circuit structure of claim 19, wherein:

the logic circuitry of the at least one controller substrate is tested by an external means; and

the array of memory cells of the at least one memory substrate are tested by the logic circuitry of the at least one controller substrate, wherein the testing achieves a functional testing of a substantial portion of the array of memory cells.

24. The integrated circuit structure of claim 19, wherein the logic circuitry of the at least one controller substrate performs functional testing of a substantial portion of the array of memory cells.

25. The integrated circuit structure of claim 19, wherein the controller substrate logic is further configured to:

prevent the use of at least one defective gate line; and

replace references to memory cells addressed using the defective gate line with references to spare memory cells addressed using a spare gate line.

26. The integrated circuit structure of claim 19, wherein the controller substrate logic is further configured to prevent the use of at least one defective gate line.

27. The integrated circuit structure of claim 19, wherein the logic circuitry of the at least one controller substrate can perform all functional testing of the array of memory cells of the at least one memory substrate.

28. The integrated circuit structure of claim 1, wherein the first substrate is a non-semiconductor material.

29. The integrated circuit structure of claim 1, wherein the first substrate and the second substrate are the same size or overlap each other completely.

30. The integrated circuit structure of claim 1, wherein at least one of the first and second substrates comprises a low stress dielectric layer, wherein the low stress dielectric layer is at least one of a silicon dioxide dielectric and an oxide of silicon dielectric and is caused to have a stress of about 5×

10⁸ dynes/cm² or less.

31. The integrated circuit structure of claim 1, further comprising memory circuitry on the second substrate, wherein a portion of the memory circuitry is redundant memory circuitry.

32. The integrated circuit structure of claim 1, wherein at least two of:

the first substrate is a non-semiconductor material;

at least one of said surfaces of the second substrate has formed thereon a dielectric with a stress of about 5×

10⁸ dynes/cm² or less;

the dielectric is at least one of silicon dioxide and an oxide of silicon;

the second substrate has one of logic circuitry and memory circuitry formed thereon;

the second substrate has microprocessor circuitry formed thereon;

the second substrate has reconfiguration circuitry formed thereon;

the second substrate has redundant circuitry formed thereon;

the second substrate has a thickness of about 1 to 8 microns;

the second substrate has a thickness of about 10 microns or less;

the first substrate and the second substrate are bonded by at least one diffusion bond;

at least one of the substrates is substantially flexible;

the second substrate is substantially flexible;

at least one conductive path passes through the first substrate;

at least one conductive path passes through the second substrate;

at least one conductive path passes through the second substrate between the first surface and the second surface of the second substrate;

at least one conductive path passes through the second substrate between interconnect contacts on the first surface and the second surface of the second substrate;

conductive paths are formed between and within overlapping portions of bonded surfaces of the first substrate and second substrate;

the second surface of the second substrate has an oxide layer formed thereon.

33. The integrated circuit structure of claim 1, wherein at least three of:

the first substrate is a non-semiconductor material;

at least one of said surfaces of the second substrate has formed thereon a dielectric with a stress of about 5×

10⁸ dynes/cm² or less;

the dielectric is at least one of silicon dioxide and an oxide of silicon;

the second substrate has one of logic circuitry and memory circuitry formed thereon;

the second substrate has microprocessor circuitry formed thereon;

the second substrate has reconfiguration circuitry formed thereon;

the second substrate has redundant circuitry formed thereon;

the second substrate has a thickness of about 1 to 8 microns;

the second substrate has a thickness of about 10 microns or less;

the first substrate and the second substrate are bonded by at least one diffusion bond;

at least one of the substrates is substantially flexible;

the second substrate is substantially flexible;

at least one conductive path passes through the first substrate;

at least one conductive path passes through the second substrate;

at least one conductive path passes through the second substrate between the first surface and the second surface of the second substrate;

at least one conductive path passes through the second substrate between interconnect contacts on the first surface and the second surface of the second substrate;

conductive paths are formed between and within overlapping portions of bonded surfaces of the first substrate and second substrate;

the second surface of the second substrate has an oxide layer formed thereon.

34. The integrated circuit structure of claim 1, wherein at least four of:

the first substrate is a non-semiconductor material;

at least one of said surfaces of the second substrate has formed thereon a dielectric with a stress of about 5×

10⁸ dynes/cm² or less;

the dielectric is at least one of silicon dioxide and an oxide of silicon;

the second substrate has one of logic circuitry and memory circuitry formed thereon;

the second substrate has microprocessor circuitry formed thereon;

the second substrate has reconfiguration circuitry formed thereon;

the second substrate has redundant circuitry formed thereon;

the second substrate has a thickness of about 1 to 8 microns;

the second substrate has a thickness of about 10 microns or less;

the first substrate and the second substrate are bonded by at least one diffusion bond;

at least one of the substrates is substantially flexible;

the second substrate is substantially flexible;

at least one conductive path passes through the first substrate;

at least one conductive path passes through the second substrate;

at least one conductive path passes through the second substrate between the first surface and the second surface of the second substrate;

at least one conductive path passes through the second substrate between interconnect contacts on the first surface and the second surface of the second substrate;

conductive paths are formed between and within overlapping portions of bonded surfaces of the first substrate and second substrate;

the second surface of the second substrate has an oxide layer formed thereon.

35. The integrated circuit structure of claim 1, wherein the second substrate has microprocessor circuitry formed thereon.

36. The integrated circuit structure of claim 1, wherein the first substrate and the second substrate are bonded by at least one diffusion bond.

37. The integrated circuit structure of claim 1, wherein the second substrate is substantially flexible.

38. The integrated circuit structure of claim 1, wherein at least one of the substrates is substantially flexible.

39. The integrated circuit structure of claim 1, wherein at least one conductive path passes through the first substrate.

40. The integrated circuit structure of claim 1, wherein at least one conductive path passes through the second substrate.

41. The integrated circuit structure of claim 1, wherein at least one conductive path passes through the second substrate between the first surface and the second surface of the second substrate.

42. The integrated circuit structure of claim 1, wherein at least one conductive path passes through the second substrate between interconnect contacts on the first surface and the second surface of the second substrate.

43. The integrated circuit structure of claim 1, wherein conductive paths are formed between and within overlapping portions of bonded surfaces of the first substrate and second substrate.

44. An integrated circuit structure comprising:

a first substrate having topside and bottomside surfaces, wherein the topside surface of the first substrate has interconnect contacts;

a second substrate having a thickness of about 50 microns or less and having topside and bottomside surfaces, wherein at least one of the topside surface and the bottomside surface of the second substrate has interconnect contacts, and wherein the bottomside surface of the second substrate is polished;

wherein a major portion of the topside surface of the first substrate and one of the topside surface of the second substrate and the bottomside surface of the second substrate are bonded in a stacked relationship; and

conductive paths between the interconnect contacts on the topside surface of the first substrate and said one of the topside surface of the second substrate and the bottomside surface of the second substrate, the conductive paths providing electrical connections between the first substrate and the second substrate;

wherein the first substrate overlaps at least a majority of the second substrates.

45. The integrated circuit structure of claim 44, wherein selected ones of said interconnect contacts of said topside surface of said first substrate are in electrical contact with selected ones of the interconnect contacts of said bottomside surface of said second substrate so as to form said electrical connections.

46. The integrated circuit structure of claim 44, wherein the first substrate and the second substrate are the same size or overlap each other completely.

47. The integrated circuit structure of claim 44, wherein at least one of the first and second substrates comprises a low stress dielectric layer, wherein the low stress dielectric layer is at least one of a silicon dioxide dielectric and an oxide of silicon dielectric and is caused to have a stress of about 5×

10⁸ dynes/cm² or less.

48. The integrated circuit structure of claim 44, further comprising memory circuitry on the second substrate, wherein a portion of the memory circuitry is redundant memory circuitry.

49. The integrated circuit structure of claim 44, wherein at least two of:

the first substrate is a non-semiconductor material;

at least one of said surfaces of the second substrate has formed thereon a dielectric with a stress of about 5×

10⁸ dynes/cm² or less;

the dielectric is at least one of silicon dioxide and an oxide of silicon;

the second substrate has one of logic circuitry and memory circuitry formed thereon;

the second substrate has microprocessor circuitry formed thereon;

the second substrate has reconfiguration circuitry formed thereon;

the second substrate has redundant circuitry formed thereon;

the second substrate has a thickness of about 1 to 8 microns;

the second substrate has a thickness of about 10 microns or less;

the first substrate and the second substrate are bonded by at least one diffusion bond;

at least one of the substrates is substantially flexible;

the second substrate is substantially flexible;

at least one conductive path passes through the first substrate;

at least one conductive path passes through the second substrate;

at least one conductive path passes through the second substrate between the first surface and the second surface of the second substrate;

at least one conductive path passes through the second substrate between interconnect contacts on the first surface and the second surface of the second substrate;

conductive paths are formed between and within overlapping portions of bonded surfaces of the first substrate and second substrate;

the bottomside surface of the second substrate has an oxide layer formed thereon.

50. The integrated circuit structure of claim 44, wherein at least three of:

the first substrate is a non-semiconductor material;

at least one of said surfaces of the second substrate has formed thereon a dielectric with a stress of about 5×

10⁸ dynes/cm² or less;

the dielectric is at least one of silicon dioxide and an oxide of silicon;

the second substrate has one of logic circuitry and memory circuitry formed thereon;

the second substrate has microprocessor circuitry formed thereon;

the second substrate has reconfiguration circuitry formed thereon;

the second substrate has redundant circuitry formed thereon;

the second substrate has a thickness of about 1 to 8 microns;

the second substrate has a thickness of about 10 microns or less;

the first substrate and the second substrate are bonded by at least one diffusion bond;

at least one of the substrates is substantially flexible;

the second substrate is substantially flexible;

at least one conductive path passes through the first substrate;

at least one conductive path passes through the second substrate;

at least one conductive path passes through the second substrate between the first surface and the second surface of the second substrate;

at least one conductive path passes through the second substrate between interconnect contacts on the first surface and the second surface of the second substrate;

conductive paths are formed between and within overlapping portions of bonded surfaces of the first substrate and second substrate;

the bottomside surface of the second substrate has an oxide layer formed thereon.

51. The integrated circuit structure of claim 44, wherein at least four of:

the first substrate is a non-semiconductor material;

the at least one of said surfaces of the second substrate has formed thereon a dielectric with a stress of about 5×

10⁸ dynes/cm² or less;

the dielectric is at least one of silicon dioxide and an oxide of silicon;

the second substrate has one of logic circuitry and memory circuitry formed thereon;

the second substrate has microprocessor circuitry formed thereon;

the second substrate has reconfiguration circuitry formed thereon;

the second substrate has redundant circuitry formed thereon;

the second substrate has a thickness of about 1 to 8 microns;

the second substrate has a thickness of about 10 microns or less;

the first substrate and the second substrate are bonded by at least one diffusion bond;

at least one of the substrates is substantially flexible;

the second substrate is substantially flexible;

at least one conductive path passes through the first substrate;

at least one conductive path passes through the second substrate;

at least one conductive path passes through the second substrate between the first surface and the second surface of the second substrate;

at least one conductive path passes through the second substrate between interconnect contacts on the first surface and the second surface of the second substrate;

conductive paths are formed between and within overlapping portions of bonded surfaces of the first substrate and second substrate;

the bottomside surface of the second substrate has an oxide layer formed thereon.

52. The integrated circuit structure of claim 44, wherein the first substrate is a non-semiconductor substrate.

53. The integrated circuit structure of claim 44, wherein the second substrate has microprocessor circuitry formed thereon.

54. The integrated circuit structure of claim 44, wherein the second substrate is one of a thin monocrystalline semiconductor substrate and a thin polycrystalline semiconductor substrate.

55. The integrated circuit structure of claim 44, wherein the circuitry formed on the second substrate is one of active circuitry and passive circuitry.

56. The integrated circuit structure of claim 44, wherein the circuitry formed on the second substrate comprises both active circuitry and passive circuitry.

57. The integrated circuit structure of claim 44, wherein the first substrate is a substrate having circuitry formed thereon.

58. The integrated circuit structure of claim 57, wherein the circuitry of the first substrate comprises one of active circuitry and passive circuitry.

59. The integrated circuit structure of claim 57, wherein the circuitry of the first substrate comprises both active circuitry and passive circuitry.

60. The integrated circuit structure of claim 44, wherein the first substrate and the second substrate are bonded by at least one diffusion bond.

61. The integrated circuit structure of claim 44, wherein at least one of the substrates is substantially flexible.

62. The integrated circuit structure of claim 44, wherein the second substrate is substantially flexible.

63. The integrated circuit structure of claim 44, wherein at least one conductive path passes through the first substrate.

64. The integrated circuit structure of claim 44, wherein at least one conductive path passes through the second substrate.

65. The integrated circuit structure of claim 44, wherein at least one conductive path passes through the second substrate between the topside surface and the bottomside surface of the second substrate.

66. The integrated circuit structure of claim 44, wherein at least one conductive path passes through the second substrate between interconnect contacts on the topside surface and the bottomside surface of the second substrate.

67. The integrated circuit structure of claim 44, wherein conductive paths are formed between and within overlapping portions of bonded surfaces of the first substrate and second substrate.

68. The integrated circuit structure of claim 44, further comprising:

at least one additional thin substrate having circuitry formed thereon;

a first of said at least one additional thin substrate being bonded to the second substrate and any additional thin substrates being bonded to a directly adjacent additional thin substrate; and

conductive paths formed between said first of said at least one additional thin substrate and at least one of said first and second substrates and also between each additional thin substrate and at least one of said substrates of the integrated circuit structure.

69. The integrated circuit structure of claim 68, further comprising:

at least one controller substrate having logic circuitry formed thereon;

at least one memory substrate having memory circuitry formed thereon;

a plurality of data lines and a plurality of gate lines on each memory substrate;

an array of memory cells on each memory substrate, wherein each memory cell stores a data value and has circuitry that couples the data value to one of the plurality of data lines in response to selecting one of the plurality of gate lines;

a gate line selection circuit that enables a gate line for a memory operation, wherein the gate line selection circuit comprises programmable gates for receiving address assignments for at least one gate line of the plurality of gate lines and wherein the address assignments are for determining which of the plurality of gate lines is selected for each address assignment; and

controller substrate logic that determines if at least one memory cell of the array of memory cells is defective and alters the address assignments of the plurality of gate lines to remove references to the gate line that causes the defective memory cell to couple a data value to one of the plurality of data lines.

70. The integrated circuit structure of claim 69, wherein the controller substrate logic is configured to:

test the array of memory cells periodically to determine if at least one of the array of memory cells is defective; and

removes references in the address assignments to gate lines that cause detected defective memory cells to couple data values to the plurality of data lines.

71. The integrated circuit structure of claim 69, further comprising:

programmable logic to prevent the use of data values from the plurality of data lines when gate lines cause detected defective memory cells to couple data values to the plurality of data lines.

72. The integrated circuit structure of claim 69, wherein the array of memory cells are arranged within physical space in a physical order and are arranged within an address space in a logical order and wherein the physical order of at least one memory cell is different than the logical order of the at least one memory cell.

73. The integrated circuit structure of claim 69, wherein:

the logic circuitry of the at least one controller substrate is tested by an external means; and

the array of memory cells of the at least one memory substrate are tested by the logic circuitry of the at least one controller substrate, wherein the testing achieves a functional testing of a substantial portion of the array of memory cells.

74. The integrated circuit structure of claim 69, wherein the logic circuitry of the at least one controller substrate performs functional testing of a substantial portion of the array of memory cells.

75. The integrated circuit structure of claim 69, wherein the controller substrate logic is further configured to:

prevent the use of at least one defective gate line; and

replace references to memory cells addressed using the defective gate line with references to spare memory cells addressed using a spare gate line.

76. The integrated circuit structure of claim 69, wherein the controller substrate logic is further configured to prevent the use of at least one defective gate line.

77. The integrated circuit structure of claim 69, wherein the logic circuitry of the at least one controller substrate can perform all functional testing of the array of memory cells of the at least one memory substrate.

78. The integrated circuit structure of claim 68, wherein at least two of the first, the second and the at least one additional thin substrates are formed using different respective process technologies, wherein the different respective process technologies are selected from the group consisting of a DRAM process technology, a SRAM process technology, a FLASH process technology, an EPROM process technology, an EEPROM process technology, a Ferroelectric process technology and a Giant Magneto Resistance process technology.

79. The integrated circuit structure of claim 68, wherein at least one of the first, the second and the at least one additional thin substrates comprises a microprocessor.

80. The integrated circuit structure of claim 68, wherein:

at least one substrate of the first, the second and the at least one additional thin substrates has memory circuitry formed thereon; and

at least one substrate of the first, the second and the at least one additional thin substrates has logic circuitry formed thereon that performs tests on the at least one substrate that has memory circuitry formed thereon.

81. The integrated circuit structure of claim 68, wherein at least one substrate of the first, the second and the at least one additional thin substrates has memory circuitry formed thereon, the memory circuitry having a plurality of memory locations, wherein at least one memory location of the plurality of memory locations is used for sparing and wherein data from the at least one memory location on the at least one substrate having memory circuitry formed thereon is used instead of data from a defective memory location on the at least one substrate that has memory circuitry formed thereon.

82. The integrated circuit structure of claim 68, wherein:

at least one substrate of the first, the second and the at least one additional thin substrates has memory circuitry formed thereon; and

at least one substrate of the first, the second and the at least one additional thin substrates has logic circuitry formed thereon that performs programmable gate line address assignment with respect to the at least one substrate having memory circuitry formed thereon.

83. The integrated circuit structure of claim 68, further comprising a plurality of interior vertical interconnections that traverse at least one of the first, the second and the at least one additional thin substrates.

84. The integrated circuit structure of claim 68, wherein information processing is performed on data routed between the circuitry of at least two of the first, the second and the at least one additional thin substrates.

85. The integrated circuit structure of claim 68, wherein at least one of the first, the second and the at least one additional thin substrates comprises reconfiguration circuitry.

86. The integrated circuit structure of claim 68, wherein at least one of the first, the second, and the at least one additional thin substrates has logic circuitry formed thereon for performing at least one function from the group consisting of:

virtual memory management, ECC, indirect addressing, content addressing, data compression, data decompression, graphics acceleration, audio encoding, audio decoding, video encoding, video decoding, voice recognition, handwriting recognition, power management and database processing.

87. The integrated circuit structure of claim 68, further comprising:

a memory array having a plurality of memory storage cells, a plurality of data lines, and a plurality of gate lines, wherein each memory storage cell stores a data value and has circuitry for coupling the data value to one of the plurality of data lines in response to receiving a gate control signal from one of the plurality of gate lines;

circuitry that generates the gate control signal in response to receiving an address, including means for mapping addresses to gate lines; and

a controller that determines if at least one of the plurality of memory cells is defective and alters said mapping to remove references to the one of the plurality of memory cells that is defective.

88. An integrated circuit structure comprising:

a first substrate having a first and second surface;

a second substrate having a first and second surface, wherein said second surfaces of the first and second substrates are opposite to said first surfaces;

wherein at least one of the first substrate and the second substrate has a thickness of about 50 microns or less, thereby providing at least one thin substrate, and wherein the second surface of the at least one thin substrate is polished;

wherein the first surface of the first substrate and a major portion of one of the first surface of the second substrate and the second surface of the second substrate are bonded in a stacked relationship by at least one bond, wherein the at least one bond secures a major portion of the second substrate to the first substrate; and

conductive paths between at least two of the first surface of the first substrate and the first and second surfaces of the second substrate, wherein the first substrate overlaps at least a majority of the second substrate.

89. The integrated circuit structure of claim 88, wherein the first substrate and the second substrate are the same size or overlap each other completely.

90. The integrated circuit structure of claim 88, wherein at least one of the first and second substrates comprises a low stress dielectric layer, wherein the low stress dielectric layer is at least one of a silicon dioxide dielectric and an oxide of silicon dielectric and is caused to have a stress of about 5×

10⁸ dynes/cm 2 or less.

91. The integrated circuit structure of claim 88, further comprising memory circuitry on the second substrate, wherein a portion of the memory circuitry is redundant memory circuitry.

92. The integrated circuit structure of claim 88, wherein at least two of:

the first substrate is a non-semiconductor material;

at least one of said surfaces of the second substrate has formed thereon a dielectric with a stress of about 5×

10⁸ dynes/cm² or less;

the dielectric is at least one of silicon dioxide and an oxide of silicon;

the second substrate has one of logic circuitry and memory circuitry formed thereon;

the second substrate has microprocessor circuitry formed thereon;

the second substrate has reconfiguration circuitry formed thereon;

the second substrate has redundant circuitry formed thereon;

the second substrate has a thickness of about 1 to 8 microns;

the second substrate has a thickness of about 10 microns or less;

the first substrate and the second substrate are bonded by at least one diffusion bond;

at least one of the substrates is substantially flexible;

the second substrate is substantially flexible;

at least one conductive path passes through the first substrate;

at least one conductive path passes through the second substrate;

at least one conductive path passes through the first substrate between the first surface and the second surface of the first substrate;

at least one conductive path passes through the second substrate between the first surface and the second surface of the second substrate;

conductive paths are formed between and within overlapping portions of bonded surfaces of the first substrate and second substrate;

the second surface of the second substrate has an oxide layer formed thereon.

93. The integrated circuit structure of claim 88, wherein at least three of:

the first substrate is a non-semiconductor material;

at least one of said surfaces of the second substrate has formed thereon a dielectric with a stress of about 5×

10⁸ dynes/cm² or less;

the dielectric is at least one of silicon dioxide and an oxide of silicon;

the second substrate has one of logic circuitry and memory circuitry formed thereon;

the second substrate has microprocessor circuitry formed thereon;

the second substrate has reconfiguration circuitry formed thereon;

the second substrate has redundant circuitry formed thereon;

the second substrate has a thickness of about 1 to 8 microns;

the second substrate has a thickness of about 10 microns or less;

the first substrate and the second substrate are bonded by at least one diffusion bond;

at least one of the substrates is substantially flexible;

the second substrate is substantially flexible;

at least one conductive path passes through the first substrate;

at least one conductive path passes through the second substrate;

at least one conductive path passes through the first substrate between the first surface and the second surface of the first substrate;

at least one conductive path passes through the second substrate between the first surface and the second surface of the second substrate;

conductive paths are formed between and within overlapping portions of bonded surfaces of the first substrate and second substrate;

the second surface of the second substrate has an oxide layer formed thereon.

94. The integrated circuit structure of claim 88, wherein at least four of:

the first substrate is a non-semiconductor material;

at least one of said surfaces of the second substrate has formed thereon a dielectric with a stress of about 5×

10⁸ dynes/cm² or less;

the dielectric is at least one of silicon dioxide and an oxide of silicon;

the second substrate has one of logic circuitry and memory circuitry formed thereon;

the second substrate has microprocessor circuitry formed thereon;

the second substrate has reconfiguration circuitry formed thereon;

the second substrate has redundant circuitry formed thereon;

the second substrate has a thickness of about 1 to 8 microns;

the second substrate has a thickness of about 10 microns or less;

the first substrate and the second substrate are bonded by at least one diffusion bond;

at least one of the substrates is substantially flexible;

the second substrate is substantially flexible;

at least one conductive path passes through the first substrate;

at least one conductive path passes through the second substrate;

at least one conductive path passes through the first substrate between the first surface and the second surface of the first substrate;

at least one conductive path passes through the second substrate between the first surface and the second surface of the second substrate;

conductive paths are formed between and within overlapping portions of bonded surfaces of the first substrate and second substrate;

the second surface of the second substrate has an oxide layer formed thereon.

95. The integrated circuit structure of claim 88, wherein the second substrate has microprocessor circuitry formed thereon.

96. The integrated circuit structure of claim 88, wherein the second substrate is one of a thin monocrystalline semiconductor substrate and a thin polycrystalline semiconductor substrate.

97. The integrated circuit structure of claim 88, wherein the circuitry formed on the second substrate is one of active circuitry and passive circuitry.

98. The integrated circuit structure of claim 88, wherein the circuitry formed on the second substrate comprises both active circuitry and passive circuitry.

99. The integrated circuit structure of claim 88, wherein the first substrate is a substrate having circuitry formed thereon.

100. The integrated circuit structure of claim 99, wherein the circuitry of the first substrate comprises one of active circuitry and passive circuitry.

101. The integrated circuit structure of claim 99, wherein the circuitry of the first substrate comprises both active circuitry and passive circuitry.

102. The integrated circuit structure of claim 88, further comprising:

at least one additional thin substrate having circuitry formed thereon;

a first of said at least one additional thin substrate being bonded to the second substrate and any additional thin substrates being bonded to a directly adjacent additional thin substrate; and

conductive paths formed between said first of said at least one additional thin substrate and at least one of said first and second substrates and also between each additional thin substrate and at least one of said substrates of the integrated circuit structure.

103. The integrated circuit structure of claim 102, wherein at least two of the first, the second and the at least one additional thin substrates are formed using different respective process technologies, wherein the different respective process technologies are selected from the group consisting of a DRAM process technology, a SRAM process technology, a FLASH process technology, an EPROM process technology, an EEPROM process technology, a Ferroelectric process technology and a Giant Magneto Resistance process technology.

104. The integrated circuit structure of claim 102, wherein at least one of the first, the second and the at least one additional thin substrates comprises a microprocessor.

105. The integrated circuit structure of claim 102, wherein:

at least one substrate of the first, the second and the at least one additional thin substrates has memory circuitry formed thereon; and

at least one substrate of the first, the second and the at least one additional thin substrates has logic circuitry formed thereon that performs tests on the at least one substrate that has memory circuitry formed thereon.

106. The integrated circuit structure of claim 102, wherein at least one substrate of the first, the second and the at least one additional thin substrates has memory circuitry formed thereon, the memory circuitry having a plurality of memory locations, wherein at least one memory location of the plurality of memory locations is used for sparing and wherein data from the at least one memory location on the at least one substrate having memory circuitry formed thereon is used instead of data from a defective memory location on the at least one substrate that has memory circuitry formed thereon.

107. The integrated circuit structure of claim 102, wherein:

at least one substrate of the first, the second and the at least one additional thin substrates has memory circuitry formed thereon; and

at least one substrate of the first, the second and the at least one additional thin substrates has logic circuitry formed thereon that performs programmable gate line address assignment with respect to the at least one substrate having memory circuitry formed thereon.

108. The integrated circuit structure of claim 102, further comprising a plurality of interior vertical interconnections that traverse at least one of the first, the second and the at least one additional thin substrates.

109. The integrated circuit structure of claim 102, wherein information processing is performed on data routed between the circuitry of at least two of the first, the second and the at least one additional thin substrates.

110. The integrated circuit structure of claim 102, wherein at least one of the first, the second and the at least one additional thin substrates comprises reconfiguration circuitry.

111. The integrated circuit structure of claim 102, further comprising:

a memory array having a plurality of memory storage cells, a plurality of data lines, and a plurality of gate lines, wherein each memory storage cell stores a data value and comprises circuitry for coupling the data value to one of the plurality of data lines in response to receiving a gate control signal from one of the plurality of gate lines;

circuitry that generates the gate control signal in response to receiving an address, including means for mapping addresses to gate lines; and

a controller that determines if at least one of the plurality of memory cells is defective and alters said mapping to remove references to the one of the plurality of memory cells that is defective.

112. The integrated circuit structure of claim 102, further comprising:

at least one controller substrate having logic circuitry formed thereon;

at least one memory substrate having memory circuitry formed thereon;

a plurality of data lines and a plurality of gate lines on each memory substrate;

an array of memory cells on each memory substrate, wherein each memory cell stores a data value and comprises circuitry that couples the data value to one of the plurality of data lines in response to selecting one of the plurality of gate lines;

a gate line selection circuit that enables a gate line for a memory operation, wherein the gate line selection circuit has programmable gates for receiving address assignments for at least one gate line of the plurality of gate lines and wherein the address assignments are for determining which of the plurality of gate lines is selected for each address assignment; and

controller substrate logic that determines if at least one memory cell of the array of memory cells is defective and alters the address assignments of the plurality of gate lines to remove references to the gate line that causes the defective memory cell to couple a data value to one of the plurality of data lines.

113. The integrated circuit structure of claim 102, wherein at least one of the first, the second, and the at least one additional thin substrates has logic circuitry formed thereon for performing at least one function from the group consisting of:

virtual memory management, ECC, indirect addressing, content addressing, data compression, data decompression, graphics acceleration, audio encoding, audio decoding, video encoding, video decoding, voice recognition, handwriting recognition, power management and database processing.

114. The integrated circuit structure of claim 113, wherein the controller substrate logic is configured to:

tests the array of memory cells periodically to determine if at least one of the array of memory cells is defective; and

removes references in the address assignments to gate lines that cause detected defective memory cells to couple data values to the plurality of data lines.

115. The integrated circuit structure of claim 113, further comprising:

programmable logic to prevent the use of data values from the plurality of data lines when gate lines cause detected defective memory cells to couple data values to the plurality of data lines.

116. The integrated circuit structure of claim 113, wherein the array of memory cells are arranged within physical space in a physical order and are arranged within an address space in a logical order and wherein the physical order of at least one memory cell is different than the logical order of the at least one memory cell.

117. The integrated circuit structure of claim 113, wherein:

the logic circuitry of the at least one controller substrate is tested by an external means; and

the array of memory cells of the at least one memory substrate are tested by the logic circuitry of the at least one controller substrate, wherein the testing achieves a functional testing of a substantial portion of the array of memory cells.

118. The integrated circuit structure of claim 113, wherein the logic circuitry of the at least one controller substrate performs functional testing of a substantial portion of the array of memory cells.

119. The integrated circuit structure of claim 113, wherein the controller substrate logic is further configured to:

prevent the use of at least one defective gate line; and

replace references to memory cells addressed using the defective gate line with references to spare memory cells addressed using a spare gate line.

120. The integrated circuit structure of claim 113, wherein the controller substrate logic is further configured to prevent the use of at least one defective gate line.

121. The integrated circuit structure of claim 113, wherein the logic circuitry of the at least one controller substrate can perform all functional testing of the array of memory cells of the at least one memory substrate.

122. The integrated circuit structure of claim 88, wherein the first substrate is a non-semiconductor material.

123. The integrated circuit structure of claim 88, wherein the first substrate and the second substrate are bonded by at least one diffusion bond.

124. The integrated circuit structure of claim 88, wherein at least one of the substrates is substantially flexible.

125. The integrated circuit structure of claim 88, wherein the second substrate is substantially flexible.

126. The integrated circuit structure of claim 88, wherein at least one conductive path passes through the first substrate.

127. The integrated circuit structure of claim 88, wherein at least one conductive path passes through the second substrate.

128. The integrated circuit structure of claim 88, wherein at least one conductive path passes through the first substrate between the first surface and the second surface of the first substrate.

129. The integrated circuit structure of claim 88, wherein at least one conductive path passes through the second substrate between the first surface and the second surface of the second substrate.

130. The integrated circuit structure of claim 88, wherein conductive paths are formed between and within overlapping portions of bonded surfaces of the first substrate and second substrate.