Measuring and identifying analog characteristics of a microelectronic component at a wafer level and a platform level

• US 7,705,620 B2
• Filed: 03/29/2006
• Issued: 04/27/2010
• Est. Priority Date: 03/29/2006
• Status: Expired due to Fees

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Kenton, Jonathan, Wong, Iris, Kelkar, Mukul, Volk, Andy
• Primary Examiner(s): Nguyen; Ha Tran T
• Assistant Examiner(s): Nguyen; Tung X
• Application Number:
  US11/393,468
• Publication Number:
  US 20070229106A1
• Time in Patent Office: 1,490 Days
• Field of Search: 324/765, 324/754, 324761-762, 324/158.1, 324/763, 257/48, 438/14, 438 17- 18
• US Class Current: 324/750.3
• CPC Class Codes: G01R 31/318511 Wafer Test

Abstract

A die includes circuit components to perform normal operations and duplicated components of selective ones of the circuit components. Each end of the duplicated components is connected to a pad on the die to allow access by measurement devices. The measurement devices apply electricity to the pads to measure analog characteristics of the duplicated components.

Claims

1. A method comprising:

disabling access to an operational circuit on a die, which is an integrated circuit chip that contains both the operational circuit and a test circuit, the operational circuit sharing same pads with a test circuit that includes a plurality of duplicated components that are duplicates of circuit components in the die;

selecting, with one or more multiplexers, from the plurality of duplicated components a selected duplicated component;

electrically connecting ends of the selected duplicated component to the pads on the die;

applying electricity to the pads to measure characteristics of the selected duplicated component; and

calibrating a loss in a signal path defined by the selected duplicated component.

2. The method of claim 1 wherein selecting from the plurality of duplicated components a selected duplicated component further comprises:

connecting each of the ends of the selected duplicated component to one of the pads through one of the multiplexers to form a signal path.

3. The method of claim 1 further comprising:

triggering a test mode before applying the electricity by performing a configuration write into Design for Testability Unit configuration registers.

4. The method of claim 1 further comprising:

triggering a test mode when a number of the pads on the die are in a predefined state or a predefined sequence of states.

5. The method of claim 1 further comprising:

calibrating a loss in a signal path defined by the selected duplicated component by subjecting the selected duplicated component to a four-point probing.

6. The method of claim 1 further comprising:

calibrating a loss in a signal path defined by the selected duplicated component by first measuring a voltage drop in a short circuit connected to the multiplexers in lieu of the selected duplicated component.

7. The method of claim 1 wherein applying electricity further comprises:

measuring analog characteristics of the selected duplicated component.

8. The method of claim 1 wherein applying electricity further comprises:

applying electricity to the pads at a wafer level and at a platform level.

9. The method of claim 1, wherein the duplicated components include at least one component from the following:

a resistor, a transistor, a diode, and a capacitor.

10. The method of claim 1, wherein disabling access to an operational circuit further comprises:

tristating output buffers associated with the pads to disable the operational circuit from driving the pads.

11. The method of claim 1, wherein disabling access to an operational circuit further comprises:

disabling input to the operational circuit or logically gating an output of input buffers associated with the pads.