Programmable logic device having logic elements with dedicated hardware to configure look up tables as registers

• US 7,705,628 B1
• Filed: 07/12/2006
• Issued: 04/27/2010
• Est. Priority Date: 03/31/2006
• Status: Expired due to Fees

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Baeckler, Gregg William, Hutton, Michael D., Yuan, Jinyong, Lee, Andy L., Duwel, Keith
• Primary Examiner(s): Tan; Vibol
• Assistant Examiner(s): Tabler; Matthew C
• Application Number:
  US11/486,164
• Time in Patent Office: 1,385 Days
• Field of Search: 326 37- 50
• US Class Current: 326/41
• CPC Class Codes: H03K 19/173 using elementary logic circuits as components
• CPC Class Codes: H03K 19/1736 in which the wiring can be modified
• CPC Class Codes: H03K 19/17728 Reconfigurable logic blocks, e.g. lookup tables

Abstract

A programmable logic device architecture having logic elements with dedicated hardware to configure the look up tables of the logic element to either perform logic functions or to operate as a register for pipelining or other purposes. The programmable logic device includes a general interconnect and a plurality of logic array blocks interconnected by the general interconnect. Each of the plurality of logic blocks further includes one or more logic elements. The logic elements each include a first look up table, a second look up table, and dedicated hardware within the logic element to configure the first look table and the second look up table as a register without having to use the general interconnect. In one embodiment, the dedicated hardware includes a plurality of dedicated interconnects within the logic element to configure the two look up tables as a pair of cross coupled muxes or latches when configured as a register.

Claims

1. A programmable logic device, comprising:

a general interconnect;

a plurality of logic array blocks (LAB) interconnected by the general interconnect;

each of the plurality of logic blocks further comprising one or more logic elements, each of the logic elements comprising;

a first look up table configured to generate an output signal, the first look up table having a first look up table input;

a second look up table configured to receive the output signal as input;

dedicated hardware within the logic element to configure the first look up table and the second look up table as a register without having to use the general interconnect;

a selection device coupled to the first look up table input and configured to select between the output signal and another signal to provide the selection to the first look up table input,

wherein the dedicated hardware includes a first dedicated interconnect providing a clock signal as an input to the first look up table and the second look up table respectively, wherein the first dedicated interconnect is connected to a LAB wide interconnect of the logic block,

wherein the first look up table is physically arranged above the second look up table in the logic block, the dedicated hardware further configured to cascade the register formed from the first look up table and the second look up table with a second register provided in the logic block.

2. The programmable logic device of claim 1, wherein the dedicated hardware within the logic element is further configured to implement the first look up table and the second look up table as cross coupled latches when configured as the register.

3. The programmable logic device of claim 1, wherein the first look up table is configured as a first latch and the second look up table is configured as a second latch when the first look up table and the second look up table are configured as the register.

4. The programmable logic device of claim 1, wherein the dedicated hardware further comprises a second dedicated interconnect provided between an output of the first look up table and an input of the first look up table.

5. The programmable logic device of claim 4, wherein the selection device comprises a first selection mux, provided on the second dedicated interconnect, to enable the selection of either the output of the first look up table or another signal to the first look up table.

6. The programmable logic device of claim 5, wherein the dedicated hardware further comprises a third dedicated interconnect provided between an output of the second look up table and an input of the second look up table.

7. The programmable logic device of claim 6, further comprising a second selection mux, provided on the third dedicated interconnect, to enable the selection of either the output of the second look up table or a general input to the second look up table.

8. The programmable logic device of claim 7, wherein the dedicated hardware further comprises a fourth dedicated interconnect provided between an output of the first look up table and an input of the second look up table.

9. The programmable logic device of claim 8, further comprising a third selection mux, provided on the fourth dedicated interconnect, to enable the selection of either the output of the first look up table or a general input to the second look up table.

10. The programmable logic device of claim 1, further comprising:

a dedicated register that is associated with the first look up table and that is configured to receive the clock signal.

11. The programmable logic device of claim 10, further comprising a pair of selection muxes, provided on the first dedicated interconnect, the pair of selection muxes configured to selectively provide either the clock signal or general inputs to the first look up table and the second look up table respectively.

23. The programmable logic device of claim 1, wherein the first look up table is configured to receive a first clock signal and the second lookup table is configured to receive a second clock signal complementary to the first clock signal.

24. The programmable logic device of claim 1, further comprising a gate configured to implement a clear on the register.

12. A method comprising:

interconnecting a plurality of logic array blocks (LABs) by using a general interconnect, one of the logic array blocks comprises at least one logic element;

receiving an output signal by a first look up table of one of the at least one logic element, said receiving the output signal is performed by a second look up table of the one of the at least one logic element;

configuring the first look table and the second look up table as a register without having to use the general interconnect, said configuring the first look up table and the second look up table as a register is performed by using dedicated hardware within the one of the at least one logic element;

selecting between the output signal and another signal to provide the selection to a single input of the first look up table;

communicating a clock signal as an input to the first look up table and the second look up table respectively, said communicating the clock signal as the input to the first look up table and the second look up table respectively is performed using a first dedicated interconnect of the dedicated hardware, wherein the first dedicated interconnect is connected to a LAB wide interconnect of one of the logic array blocks;

physically arranging the first look up table above the second look up table in the logic block, the dedicated hardware further configured to cascade the register formed from the first look up table and the second look up table with a second register in the logic block.

13. The method of claim 12, further comprising implementing the first look up table and the second look up table as cross coupled muxes when configured as the register, said implementing the first look up table and the second look up table as cross coupled muxes is performed using the dedicated hardware.

14. The method of claim 12, further comprising configuring the first look up table as a first mux and the second look up table as a second mux when the first look up table and the second look up table are configured as the register.

15. The method of claim 12, wherein the dedicated hardware further comprises a second dedicated interconnect between an output of the first look up table and an input of the first look up table.

16. The method of claim 15, wherein said selecting between the output signal and the other signal is performed by using a first selection mux on the second dedicated interconnect.

17. The method of claim 16, wherein the dedicated hardware further comprises a third dedicated interconnect provided between an output of the second look up table and an input of the second look up table.

18. The method of claim 17, further comprising selecting either the output of the second look up table or a general input as an input to the second look up table, said selecting either the output of the second look up table or the general input is performed by using a second selection mux on the third dedicated interconnect.

19. The method of claim 18, wherein the dedicated hardware further comprises a fourth dedicated interconnect between an output of the first look up table and an input of the second look up table.

20. The method of claim 19, further comprising selecting either the output of the first look up table or a general input as an input to the second look up table, wherein said selecting either the output of the first look up table or the general input is performed by using a third selection mux on the fourth dedicated interconnect.

21. The method of claim 12, further comprising:

associating a dedicated register with the first look up table, the dedicated register being configured to receive the clock signal.

22. The method of claim 12, further comprising selecting either the clock signal or general inputs to communicate to the first look up table and the second look up table respectively, said selecting either the clock signal or general inputs is performed using a pair of selection muxes on the first dedicated interconnect.