Filler circuit cell
First Claim
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1. A filler circuit cell, comprising:
- a decoupled capacitor comprising a first n-type metal-oxide semiconductor (NMOS) transistor and a first p-type metal-oxide semiconductor (PMOS) transistor, wherein the source and drain of the first NMOS transistor is connected to a second voltage source and the source and drain of the first PMOS transistor is connected to a first voltage source;
a tie low circuit disposed between the first voltage source, a gate of the first PMOS transistor and the second voltage source, wherein the tie low circuit comprises a second NMOS transistor and a second PMOS transistor; and
a tie high circuit disposed between the first voltage source, a gate of the first NMOS transistor and the second voltage source, wherein the tie high circuit comprises a third NMOS transistor and a third PMOS transistor.
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Abstract
A filler circuit cell is disclosed. The filler circuit cell includes a decoupled capacitor, a tie low circuit and a tie high circuit. The decoupled capacitor includes a first NMOS transistor and a first PMOS transistor, in which the source/drain of the first NMOS transistor is connected to a second voltage source and the source/drain of the first PMOS transistor is connected to a first voltage source. The tie low circuit includes a second NMOS transistor and a second PMOS transistor and the tie high circuit includes a third NMOS transistor and a third PMOS transistor.
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Citations
20 Claims
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1. A filler circuit cell, comprising:
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a decoupled capacitor comprising a first n-type metal-oxide semiconductor (NMOS) transistor and a first p-type metal-oxide semiconductor (PMOS) transistor, wherein the source and drain of the first NMOS transistor is connected to a second voltage source and the source and drain of the first PMOS transistor is connected to a first voltage source; a tie low circuit disposed between the first voltage source, a gate of the first PMOS transistor and the second voltage source, wherein the tie low circuit comprises a second NMOS transistor and a second PMOS transistor; and a tie high circuit disposed between the first voltage source, a gate of the first NMOS transistor and the second voltage source, wherein the tie high circuit comprises a third NMOS transistor and a third PMOS transistor. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. A filler circuit cell, comprising:
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a decoupled capacitor comprising a first MOS transistor, wherein the source and drain of the first MOS transistor is connected to a first voltage source; and a voltage stabilizing unit disposed between the first voltage source, a gate of the first MOS transistor and a second voltage source to prevent damage for the gate of the first MOS transistor caused by sudden glitches, wherein the voltage stabilizing unit comprises a second MOS transistor and a third MOS transistor. - View Dependent Claims (13, 14, 15, 16, 17, 18, 19, 20)
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Specification