Liquid crystal display of line-on-glass type

• US 7,705,820 B2
• Filed: 11/27/2002
• Issued: 04/27/2010
• Est. Priority Date: 12/22/2001
• Status: Expired due to Fees

• Current Assignee: LG Display Co., Ltd.
• Original Assignee: LG Display Co., Ltd.
• Inventors: Park, Jung Sik
• Primary Examiner(s): Beck; Alexander S.
• Application Number:
  US10/304,704
• Publication Number:
  US 20030117566A1
• Time in Patent Office: 2,708 Days
• Field of Search: 345/52, 345/63, 345/211, 345/212, 345 87-104, 345/204, 349149-152, 330/207.A
• US Class Current: 345/100
• CPC Class Codes: G02F 1/13452 Conductors connecting driver circuitry and terminals of panels
• CPC Class Codes: G09G 3/3677 suitable for active matrices only

Abstract

A line-on-glass type liquid crystal display device capable of preventing voltage differences between separate gate driver integrated circuits due to line resistances of LOG-signal line patterns includes a picture display area having a plurality of liquid crystal cells, gate driver integrated circuits for driving gate lines, line-on-glass type signal lines provided at an area outside the picture display area for applying driving signals to the gate driver integrated circuits, wherein each of the gate drive integrated circuits includes a gate input line resistor having a predetermined resistance value connected to each gate line. A resistance value of the gate input line resistors incrementally increases by a predetermined amount until a line resistance value of the line-on-glass type signal line connected between the gate driver integrated circuits is reached.

Claims

1. A line-on-glass liquid crystal display device, comprising:

a picture display area having a plurality of liquid crystal cells arranged at crossings of a plurality of gate lines and a plurality of data lines;

a plurality of gate driver integrated circuits for driving the gate lines mounted on a plurality of gate tape carrier packages, each of plurality of gate driver integrated circuits including a plurality of stages for sequentially driving the gate lines using a control signal generated by a timing controller, each of the plurality of consecutive stages being electrically connected to one of the plurality of gate lines;

a plurality of data driver integrated circuits for driving the data lines mounted on a plurality of data tape carrier packages; and

a plurality of line-on-glass signal lines provided at an outer portion of the picture display area for applying driving signals to the gate driver integrated circuits,

wherein each of plurality of gate driver integrated circuits includes a plurality of gate input line resistors each connected to one of the plurality of the stages, each of the plurality of gate input line resistors having a resistance value corresponding to the gate line it is connected to, wherein resistance values of successive gate input line resistors increases by a predetermined amount, the predetermined amount being selected such that an input line resistance value of the last gate line connected to each gate driver integrated circuit is substantially equal to an input line resistance value of the first gate line connected to a successive gate driver integrated circuit due to a line resistance of the line-on-glass signal line group between the gate driver integrated circuits.

2. The line-on-glass liquid crystal display device according to claim 1, wherein

the plurality of gate input line resistors are provided too at least one of a gate high voltage input line and a gate low voltage input line;

each gate input resister is connected between two adjacent stages for sequentially driving the gate lines within the plurality of gate driver integrated circuits; and

the resistance value of the plurality of gate input line resistors is incrementally increased by a predetermined amount for each stage.

3. The line-on-glass liquid crystal display device according to claim 1, wherein

each of the gate input line resistors is connected between a gate line and an output line of the plurality of stages for sequentially driving gate lines within the plurality of gate driver integrated circuits;

and

the resistance value of the plurality of gate input line resistors is incrementally increased by a predetermined amount at each output line.

4. The line-on-glass liquid crystal display device according to claim 1, wherein each stage comprising:

a shift register for shifting and outputting a gate start pulse signal in response to a gate shift clock signal;

a level shifter for selectively outputting a gate high or gate low voltage in response to the shift signal outputted from the shift register; and

an output buffer for buffering an output signal of the level shifter and outputting the output signal to a corresponding gate line.

5. A liquid crystal display device, comprising:

a plurality of gate lines;

a plurality of driver integrated circuits connected to the plurality of gate lines; and

a plurality of consecutive stages for sequentially driving the gate lines using a control signal generated by a timing controller, each of the plurality of consecutive stages within each of the plurality of driver integrated circuits, each of the plurality of consecutive stages being electrically connected to one of the plurality of gate lines; and

a plurality of resistors each connected to one of the plurality of stages, wherein a line resistance of successive ones of the plurality of stages is incrementally increased by a predetermined amount, the predetermined amount being selected such that a line resistance at a last one of the consecutive stages within one of the plurality of driver integrated circuits is substantially equal to a line resistance at a first one of consecutive stages within a successive one of the plurality of driver integrated circuits due to a line resistance of a signal line group between the plurality of driver integrated circuits.

6. The liquid crystal display device according to claim 5, wherein the plurality of driver integrated circuits comprise gate driver integrated circuits.

7. The liquid crystal display device according to claim 5, further comprising:

at least one voltage input line commonly connected to the plurality of stages; and

a plurality of output lines each connected to one of the plurality of stages and a corresponding one of the plurality of gate lines.

8. The liquid crystal display device according to claim 7, further comprising a plurality of resistors each arranged between two adjacent stages of the plurality of stages, wherein a resistance value of successive ones of the plurality of resistors is incrementally increased by the predetermined amount.

9. The liquid crystal display device according to claim 7, further comprising a plurality of resistors each arranged between a gate line and one of the plurality of output lines of the plurality of stages, wherein a resistance value of successive ones of the plurality of resistors is incrementally increased by the predetermined amount.

10. The liquid crystal display device according to claim 5, wherein each stage comprising:

a shift register for shifting and outputting a gate start pulse signal in response to a gate shift clock signal;

a level shifter for selectively outputting a gate high or gate low voltage in response to the shift signal outputted from the shift register; and

an output buffer for buffering an output signal of the level shifter and outputting the output signal to a corresponding gate line.

11. A liquid crystal display, comprising:

a plurality of gate lines;

a plurality of driver integrated circuits connected to the plurality of gate lines;

a plurality of stages for sequentially driving the gate lines using a control signal generated by a timing controller within each of the plurality of driver integrated circuits, each of the plurality of stages being electrically connected to one of the plurality of gate lines; and

a plurality of line-on-glass signal lines for electrically connecting the plurality of driver integrated circuits to each other;

a plurality of resistors each connected to one of the plurality of stages, wherein a line resistance of successive ones of the plurality of stages is incrementally increased by a predetermined amount, the predetermined amount being selected such that a line resistance at a last one of consecutive stages within one of the plurality of driver integrated circuits is substantially equal to a line resistance of one of the plurality of line-on-glass signal lines between the one of the plurality of driver integrated circuits and a subsequent one of the plurality of driver integrated circuits.

12. The liquid crystal display according to claim 11, wherein the subsequent one of the plurality of driver integrated circuits is a successive one of the plurality of driver integrated circuits.

13. The liquid crystal display according to claim 11, further comprising:

at least one voltage input line commonly connected to the plurality of stages; and

a plurality of output lines each connected to one of the plurality of stages and a corresponding one of the plurality of gate lines.

14. The liquid crystal display according to claim 11, further comprising a plurality of resistors each arranged between two adjacent stages of the plurality of stages and at least one voltage input line, wherein a resistance value of successive ones of the plurality of resistors is incrementally increased by the predetermined amount.

15. The liquid crystal display according to claim 11, further comprising a plurality of resistors each arranged between a gate line and one of the plurality of output lines of the plurality of stages, wherein a resistance value of successive ones of the plurality of resistors is incrementally increased by the predetermined amount.

16. The liquid crystal display according to claim 11, wherein each stage comprising:

a shift register for shifting and outputting a gate start pulse signal in response to a gate shift clock signal;

a level shifter for selectively outputting a gate high or gate low voltage in response to the shift signal outputted from the shift register; and

an output buffer for buffering an output signal of the level shifter and outputting the output signal to a corresponding gate line.