Random signal generator

• US 7,706,529 B2
• Filed: 11/27/2001
• Issued: 04/27/2010
• Est. Priority Date: 11/28/2000
• Status: Active Grant

• Current Assignee: Stmicroelectronics France (STMicroelectronics NV)
• Original Assignee: STMicroelectronics SA (STMicroelectronics NV)
• Inventors: Marinet, Fabrice, Malherbe, Alexandre
• Primary Examiner(s): Revak; Christopher A
• Application Number:
  US09/995,258
• Publication Number:
  US 20020080965A1
• Time in Patent Office: 3,073 Days
• Field of Search: None
• US Class Current: 380/44
• CPC Class Codes: G06F 7/588 Random number generators, i.e. based on natural stochastic processes
• CPC Class Codes: G06K 19/073 Special arrangements for circuits, e.g. for protecting identification code in memory protection against unauthorised use of computer memory G06F12/14
• CPC Class Codes: G06K 19/07363 by preventing analysis of the circuit, e.g. dynamic or static power analysis or current analysis
• CPC Class Codes: H03K 3/84 Generating pulses having a predetermined statistical distribution of a parameter, e.g. random pulse generators

Abstract

A random signal generator uses a folded MOS transistor, whose drain-source current includes a random component, as an electronic noise source. The random signal generator generates a random binary signal from the random component. The invention may be applied, in particular, to smart cards.

Claims

1. A random signal generator comprising;

an electronic noise source comprising a folded MOS transistor having a drain-source current with a random component;

said folded MOS transistor comprising a drain and a source with a folded channel defined therebetween; and

a circuit for generating a digital signal based upon the random component.

2. A random signal generator according to claim 1, wherein the folded channel is S-shaped and has a size that is at a resolution limit based upon manufacturing technology.

3. A random signal generator according to claim 1, wherein the folded channel is zigzag-shaped and has a size that is at a resolution limit based upon manufacturing technology.

4. A random signal generator according to claim 1, further comprising a reference transistor connected to said folded MOS transistor, said reference transistor receiving a gate voltage and a bias current equal to a gate voltage and a bias current applied to said folded MOS transistor for causing the drain-source current therefrom to randomly vary.

5. A random signal generator according to claim 1, further comprising a comparison circuit for comparing the randomly varying drain-source current to a detection current.

6. A random signal generator according to claim 5, wherein said comparison circuit determines a difference between the randomly varying drain-source current and the detection current;

and further comprising an amplifier for amplifying the difference.

7. A random signal generator according to claim 1, wherein said circuit comprises a sampling circuit for sampling the digital signal for providing a random digital word.

8. A random signal generator according to claim 1, further comprising an integrating circuit for maintaining a gate voltage on said folded MOS transistor within a desired range of values.

9. A random signal generator circuit comprising:

a plurality of random signal generators, each random signal generator comprising

an electronic noise source comprising a folded MOS transistor having a drain-source current with a random component,

said folded MOS transistor comprising a drain and a source with a folded channel defined therebetween, and

a circuit for generating a digital signal based upon the random component; and

a logic circuit connected to said plurality of random signal generators for combining the digital signals for generating a digital number.

10. A random signal generator circuit according to claim 9, wherein the folded channel is S-shaped and has a size that is at a resolution limit based upon manufacturing technology.

11. A random signal generator circuit according to claim 9, wherein the folded channel is zigzag-shaped and has a size that is at a resolution limit based upon manufacturing technology.

12. A random signal generator circuit according to claim 9, wherein each random signal generator further comprises a reference transistor connected to said folded MOS transistor, said reference transistor receiving a gate voltage and a bias current equal to a gate voltage and a bias current applied to said folded MOS transistor for causing the drain-source current therefrom to randomly vary.

13. A random signal generator circuit according to claim 9, wherein each random signal generator further comprises a comparison circuit for comparing the randomly varying drain-source current to a detection current.

14. A random signal generator circuit according to claim 13, wherein each comparison circuit determines a difference between the randomly varying drain-source current and the detection current;

and wherein each random signal generator further comprises an amplifier for amplifying the difference.

15. A random signal generator circuit according to claim 9, wherein each circuit comprises a sampling circuit for sampling the digital signal for providing a random digital words and wherein said logic circuit generates the digital number based upon the random digital word.

16. A random signal generator circuit according to claim 9, wherein each random signal generator further comprises an integrating circuit for maintaining a gate voltage on said folded MOS transistor within a desired range.

17. A method for generating a random number from an electronic noise source, the method comprising:

providing a folded MOS transistor having a drain-source current with a random component,

the folded MOS transistor comprising a drain and a source with a folded channel defined therebetween;

generating a random digital signal based upon the random component.

18. A method according to claim 17, wherein the folded channel is S-shaped and has a size that is at a resolution limit based upon manufacturing technology.

19. A method according to claim 17, wherein the folded channel is zigzag-shaped and has a size that is at a resolution limit based upon manufacturing technology.

20. A method according to claim 17, further comprising:

providing a reference transistor connected to the folded MOS transistor; and

providing a gate voltage and a bias current to the reference transistor, the gate voltage and the bias current being equal to a gate voltage and a bias current applied to the folded MOS transistor for causing the drain-source current therefrom to randomly vary.

21. A method according to claim 17, further comprising comparing the randomly varying drain-source current to a detection current.

22. A method according to claim 21, wherein the comparing comprises determining a difference between the randomly varying drain-source current and the detection current and further comprising amplifying the difference.

23. A method according to claim 17, wherein the sampling comprises providing a random digital signal based upon the sampled random binary signal, and further comprising generating the random number based upon the random digital signal.

24. A method according to claim 17, further comprising maintaining a gate voltage on the folded MOS transistor within a desired range of values.