Methods and systems for an identifier-based memory section

• US 7,707,351 B2
• Filed: 10/31/2002
• Issued: 04/27/2010
• Est. Priority Date: 10/31/2002
• Status: Expired due to Fees

• Current Assignee: RPX Corporation
• Original Assignee: Ring Technology Enterprises of Texas LLC (IPNav)
• Inventors: Bullen, Melvin James, Lynch, William Thomas, Dodd, Steven Louis, Herbison, David James
• Primary Examiner(s): Bragdon; Reginald G
• Assistant Examiner(s): Faal; Baboucarr
• Application Number:
  US10/284,268
• Publication Number:
  US 20040088477A1
• Time in Patent Office: 2,735 Days
• Field of Search: 711/109, 711/167, 711/202, 711/118, 711/162, 711/173, 365/189.12, 365/201, 365/240, 365/221, 365/73, 714/718, 370/242, 370/250, 370/359, 370/363, 370/379, 370/392, 370/395.7, 709/217, 710/316, 725/145, 725/147, 725/92, 725/93, 725/114
• US Class Current: 711/5
• CPC Class Codes: G06F 3/0613 in relation to throughput
• CPC Class Codes: G06F 3/0656 Data buffering arrangements
• CPC Class Codes: G06F 3/067 Distributed or networked storage systems, e.g. storage area networks [SAN], network attached storage [NAS]
• CPC Class Codes: H04L 49/90 Buffering arrangements
• CPC Class Codes: H04L 49/901 using storage descriptor, e.g. read or write pointers

Abstract

A storage system that may include one or more memory devices, a memory interface device corresponding to one or more of the memory devices, which are organized in sections, and a section controller. In this system, a data request for the data may be received over a communications path by a section controller. The section controller determines the addresses in the memory devices storing the requested data, transfers these addresses to those memory devices storing the requested data, and transfers an identifier to the memory interface device. The memory device, in response, reads the data and transfers the data to its corresponding memory interface device. The memory interface device then adds to the data the identifier it received from the section controller and forwards the requested bits towards their destination, such that the data need not pass through the section controller.

Claims

1. A memory section, comprising:

one or more memory devices that store data locatable by one or more addresses, the memory devices receiving control signals;

a memory section controller that receives a request for data stored by the one or more memory devices, determines one or more addresses for the requested data, determines a destination identifier for use in forwarding the requested data to a specific destination device, and transfers a control signal to the memory devices including the determined addresses to the memory device storing the requested data;

a memory interface device that receives from the memory device the requested data stored by the memory devices, receives from the memory section controller the determined destination identifier for use in forwarding the requested data, combines the requested data and the determined destination identifier, and forwards the combined requested data and destination identifier to the specific destination device;

wherein the memory interface device further includes at least one set of shift registers interconnected in series including;

at least one set of shift registers interconnected in series that write data to the memory device,

and at least one set of shift registers interconnected in series that read data from the memory device; and

wherein data loaded into the sets of shift registers are shifted from one of the shift registers in the set to a next one of the shift registers in the set according to a clock signal, such that the shift registers maintain their shift frequency during any loading of the data between the shift registers and the memory device.

2. The memory section of claim 1, wherein the destination identifier for use in forwarding the requested data is an address for a device to which the data are to be forwarded.

3. The memory section of claim 1, wherein the destination identifier for use in forwarding the requested data is an identifier that identifies the data that are to be forwarded.

4. The memory section of claim 1, wherein the determined addresses include a starting address and number of bits to transfer;

and

the memory section controller includes an internal memory in which the starting address and number of bits to transfer are placed such that they are transferred to the memory device causing the memory device to transfer the data at the locations specified by the starting address and number of bits to transfer.

5. The memory section of claim 1, wherein the memory section sends the requested data to a switch that uses the destination identifier to forward the requested data to the destination device.

6. The memory section of claim 1, wherein the memory section controller provides test data to the memory devices, checks test data received from the memory devices and determines a fault based on the checking of the test data.

7. The storage system of claim 1, wherein the storage locations of the memory devices are partitioned into data blocks that are identifiable by a data block identifier, and wherein a data request received by the memory section includes a data block identifier that is forwarded to the memory section controller;

and wherein the memory section controller determines one or more addresses based on the data block identifier and provides the determined addresses to the one or more memory devices.

8. A method for use in a storage system, comprising:

storing data in storage locations in a memory device, the storage locations identifiable by addresses;

receiving by a memory section controller a data request for data stored by the memory device;

the memory section controller determining one or more addresses for the requested data;

the memory section controller determining a destination identifier for use in forwarding the requested data to a specific destination device;

the memory section controller transferring a control signal to the memory device the control signal including the determined addresses;

the memory section controller transferring the determined destination identifier to a memory interface device;

the memory interface device receiving from the memory device the requested data;

the memory interface device combining the destination identifier and the requested data;

the memory interface device forwarding the combined requested data and destination identifier to the specific destination device; and

wherein the memory interface device further includes at least one set of shift registers interconnected in series that writes data to the memory device, and at least one set of shift registers interconnected in series that reads data from the memory device, the method further comprising;

shifting data loaded into the sets of shift registers from one of the shift registers in the set to a next one of the shift registers in the set according to a clock signal, such that the shift registers maintain their shift frequency during any loading of the data between the shift registers and the memory device.

9. The method of claim 8, wherein the determined addresses include a starting address and number of bits to transfer, further comprising:

placing the starting address and number of bits to transfer in an internal memory of the memory section controller;

transferring the starting address and number of bits to transfer from the memory section controller to the memory device; and

the memory device transferring the data at the locations specified by the starting address and number of bits to transfer in response to receiving the starting address and number of bits to transfer.

10. The method of claim 8, further comprising:

the memory section sending the requested data to a switch that uses the destination identifier to forward the requested data to the destination device.

11. The method of claim 8, further comprising:

the memory section controller providing test data to the memory devices;

the memory the section controller receiving the test data from the memory interface devices;

the memory section controller checking the received data; and

the memory section controller determining a fault based on the checking of the test data.

12. The method of claim 8, wherein the storage locations of the memory devices are partitioned into data blocks that are identifiable by a data block identifier, and wherein a data request received by the memory section includes a data block identifier, further comprising

forwarding the data request to the memory section controller;

the memory section controller determining one or more addresses based on the data block identifier; and

the memory section controller providing the determined addresses to the one or more memory devices.

13. The method of claim 8, wherein determining a destination identifier for use in forwarding the requested data to a specific destination device comprises:

treating the destination identifier as an address for a device to which the data are to be forwarded.

14. The method of claim 8, wherein determining a destination identifier for use in forwarding the requested data to a specific destination device comprises:

treating the destination identifier as an identifier that identifies the data that are to be forwarded.