SRAM cache and flash micro-controller with differential packet interface

• US 7,707,354 B2
• Filed: 10/22/2007
• Issued: 04/27/2010
• Est. Priority Date: 08/04/1999
• Status: Expired due to Fees

• Current Assignee: Super Talent Technology, Corporation
• Original Assignee: Super Talent Electronics, Inc.
• Inventors: Shen, Ming-Shiang, Ma, Abraham C., Lee, Charles C., Chow, David Q., Yu, Frank
• Primary Examiner(s): Peugh; Brian R
• Application Number:
  US11/876,251
• Publication Number:
  US 20080098164A1
• Time in Patent Office: 918 Days
• Field of Search: None
• US Class Current: 711/103
• CPC Class Codes: G06F 12/0866 for peripheral storage systems, e.g. disk cache
• CPC Class Codes: G06F 2212/2022 Flash memory
• CPC Class Codes: G06F 2212/2515 being configurable for different purposes, e.g. as cache or non-cache memory

Abstract

A flash microcontroller has a Static Random-Access-Memory (SRAM) buffer that stores several blocks of boot code read from a flash memory. The SRAM buffer also operates as a cache of flash data after booting is complete. Cache read and write hits use the SRAM cache rather than flash memory, while old cache lines and read misses access the flash memory. Both the external host and the microcontroller are booted from boot code buffered in the SRAM buffer. A boot-loader state machine reads the flash ID and programs flash parameter registers with timing parameters for the flash memory. The flash microcontroller uses a differential interface to the external host, with a differential transceiver and a differential serial interface. Frame, packet, and encoded clock processing is also performed by the serial interface.

Claims

1. A dual-boot caching flash microcontroller comprising:

a flash bus for connecting to a flash-memory chip, the flash bus carrying address, data, and commands to the flash-memory chip;

microcontroller boot code stored in the flash-memory chip in a first block;

host boot code stored in the flash-memory chip in a host-boot block;

a static random-access memory (SRAM) buffer;

a central processing unit (CPU) for executing instructions read from the SRAM buffer;

a host interface for connecting to an external host over a host bus;

a flash-memory interface for generating flash-control signals and for buffering commands, addresses, and data to the flash bus, and for reading and writing the SRAM buffer;

a boot-loader state machine, activated by a reset signal, for activating the flash-memory interface to read the microcontroller boot code from the flash-memory chip, the boot-loader state machine writing the microcontroller boot code to the first block in the SRAM buffer;

a mapping table storing mapping entries each having a logical address from the external host and a physical address of corresponding data stored in the flash-memory chip;

a tag portion of the SRAM buffer for storing tag portions of logical addresses from the external host; and

a data portion of the SRAM buffer for caching data for locations in the flash-memory chip identified by the physical address in a matching entry in the mapping table, the matching entry also storing the logical address having a tag portion in a same cache line as data in the data portion.

2. The dual-boot caching flash microcontroller of claim 1 wherein the host interface further comprises:

a differential transceiver for sending and receiving a stream of differential data to and from the external host over the host bus;

wherein the host bus is a differential-data bus; and

a differential serial interface, coupled to the differential transceiver.

3. The dual-boot caching flash microcontroller of claim 2 wherein the differential serial interface comprises a Universal Serial Bus interface circuit, a PCI-Express interface circuit, a Serial Advanced Technology Attachment (SATA) interface circuit, or an external SATA Interface Circuit.

4. The dual-boot caching flash microcontroller of claim 2 wherein the differential serial interface comprises:

a host serializing unit, coupled to the differential transceiver;

a read FIFO for buffering read words from the host serializing unit; and

a write FIFO for buffering write words to the host serializing unit.

5. The dual-boot caching flash microcontroller of claim 4 further comprising:

a decoder, coupled to the read FIFO, for decoding a format of the read words;

a bit unstuffer for removing stuff bits from the read words;

a receive hold register for storing read words for use by the CPU

a transmit hold register for storing write words from the CPU;

a bit stuffer for inserting stuff bits from the write words; and

an encoder, coupled to the write FIFO, for encoding a format of the write words.

6. The dual-boot caching flash microcontroller of claim 5 wherein the encoder and the decoder use a not-return-to-zero-invert (NRZI) encoding format or an 8-to-10 bit encoding format.

7. The dual-boot caching flash microcontroller of claim 5 wherein the host serializing unit further comprises:

a receive deserializer, coupled to the differential transceiver, for deserializing differential data received from the host to generate read words in a parallel format; and

a transmit serializer, coupled to the differential transceiver, for serializing write words from the write FIFO to generate differential data for transmission to the host by the differential transceiver.

8. The dual-boot caching flash microcontroller of claim 7 further comprising:

a clock circuit for generating a write clock to the write FIFO; and

a delay-line phase-locked loop (PLL), receiving the write clock from the clock circuit, for generating a read clock to the read FIFO.

9. The dual-boot caching flash microcontroller of claim 8 further comprising:

a receive shift register coupled between the receive hold register and the bit unstuffer, for shifting read words; and

a transmit shift register coupled between the transmit hold register and the bit stuffer, for shifting write words.

10. The dual-boot caching flash microcontroller of claim 4 wherein the microcontroller boot code executed by the CPU activates the host interface to send the host boot code to the external host;

further comprising;

flash parameter registers for storing flash parameters indicating access timing and structure of the flash-memory chip;

wherein the boot-loader state machine reads a flash identifier from the flash-memory chip to generate the flash parameters.

11. The dual-boot caching flash microcontroller of claim 10 wherein the microcontroller boot code is temporarily stored in the data portion of the SRAM buffer during booting,

wherein the data portion of the SRAM buffer is activated for caching flash data after booting is completed.

12. The dual-boot caching flash microcontroller of claim 1 wherein the flash microcontroller is one of a plurality of flash microcontrollers that connect to a dispatch unit of a solid-state-disk (SSD) array controller that connects to the external host.

13. A differential flash microcontroller comprising:

external host differential interface means for connecting to an external host by transmission of differential data;

flash bus means for connecting to a flash memory, the flash bus means carrying address, data, and commands to the flash memory;

flash-memory controller means for generating flash-control signals and for buffering commands, addresses, and data to the flash bus means;

volatile buffer means for storing instructions in a volatile memory;

processor means for fetching and executing instructions from the volatile buffer means;

cache means, using the volatile buffer means for storage, for caching data read from the flash memory and for caching data from the external host for writing to the flash memory; and

differential transceiver means for physically transmitting differential data over differential lines to the external host, and for receiving differential data sent by the external host over the differential lines;

wherein the differential transceiver means is coupled to the external host differential interface means,

whereby differential data from the external host is cached in the volatile buffer means before writing to the flash memory.

14. The differential flash microcontroller of claim 13 further comprising:

tag means for storing a tag portion of a logical address from the external host;

wherein the volatile memory means comprises a static random-access memory (SRAM) wherein the volatile buffer means is also for initially storing boot code read from the flash memory before the volatile buffer means is used by the cache means,

whereby the volatile memory means is dual use for booting and caching.

15. The differential flash microcontroller of claim 14 wherein the differential flash microcontroller is one of a plurality of differential flash microcontrollers that connect to a dispatch unit of a solid-state-disk (SSD) controller that connects to the external host.

16. The differential flash microcontroller of claim 13 further comprising:

initial boot loader means, stored in the flash memory, for instructing the processor means to read an extended-local boot sequence means from the flash memory and to write the extended-local boot sequence means into the volatile buffer means; and

hardwired initializer means, activated by a reset signal, for activating the flash-memory controller means to read the initial boot loader means from the flash memory, and for writing the initial boot loader means as first instructions to the volatile buffer means.

17. The differential flash microcontroller of claim 16 further comprising:

external-host boot sequence means, stored in the flash memory, for transfer to the external host over the external host differential interface means, wherein the external-host boot sequence means contains instructions for execution by the external host after the external host is re-booted; and

extended-local boot sequence means, stored in the flash memory, for instructing the processor means to read the external-host boot sequence means from the flash memory and to write the external-host boot sequence means into the volatile buffer means.

18. The differential flash microcontroller of claim 17 further comprising:

flash parameter register means for storing flash parameters indicating timing and access specifications of the flash memory; and

parameter write means, activated by the hardwired initializer means, for reading a flash identifier from the flash memory, for using the flash identifier to generate flash parameters, and for writing the flash parameters to the flash parameter register means;

wherein the flash-memory controller means reads the flash parameters from the flash parameter register means to generate flash-control signals that meet the timing and access specifications of the flash memory,

whereby flash parameters are extracted during initialization.

19. The differential flash microcontroller of claim 17 further comprising:

mapping table means for storing mapping entries that associate a logical address from the external host with a physical address in the flash memory or in the volatile buffer means.

20. The differential flash microcontroller of claim 17 wherein the external host differential interface means further comprises:

a Universal Serial Bus interface circuit, a Secure Digital (SD) interface circuit, a Multi Media Card (MMC) interface circuit, a PCI-Express interface circuit, a Serial Advanced Technology Attachment (SATA) interface circuit, or an external SATA Interface Circuit.