Semiconductor device including a plurality of units and a control circuit for varying the power supplied to the plurality of units

• US 7,707,442 B2
• Filed: 01/24/2005
• Issued: 04/27/2010
• Est. Priority Date: 01/30/2004
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Kato, Kiyoshi
• Primary Examiner(s): Butler; Dennis M
• Application Number:
  US10/585,571
• Publication Number:
  US 20080238533A1
• Time in Patent Office: 1,919 Days
• Field of Search: 713/310, 713/320, 713/322, 713/323, 713/324
• US Class Current: 713/322
• CPC Class Codes: G11C 5/142 Contactless power supplies, e.g. RF, induction, or IR
• CPC Class Codes: H01L 21/2007 Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer H01L21/2011 takes precedence; bonding of semiconductor wafers to semiconductor wafers for junction formation H01L21/187
• CPC Class Codes: H01L 27/12 the substrate being other than a semiconductor body, e.g. an insulating body
• CPC Class Codes: H01L 27/13 combined with thin-film or thick-film passive components
• CPC Class Codes: H01L 29/78675 with normal-type structure, e.g. with top gate

Abstract

A semiconductor device capable of stabilizing power supply by suppressing power consumption as much as possible. The semiconductor device of the invention includes a central processing unit having a plurality of units and a control circuit, and an antenna. The control circuit includes a means for outputting, based on a power supply signal including data on power supply from an antenna (through an antenna) or a load signal obtained by an event signal supplied from each of the units, one or more of a first control signal for stopping power supply to one or more of the units, a second control signal for varying a power supply potential supplied to one or more of the units, and a third control signal for stopping supplying a clock signal to one or more of the units.

Claims

1. A semiconductor device comprising:

a central processing unit including a plurality of units and a control circuit;

an antenna;

a power supply circuit; and

a clock generation circuit,

wherein the control circuit outputs to at least one of the power supply circuit and the clock generation circuit, based on a power supply signal including data on power supply from the antenna, at least one of a first control signal for stopping power supply to at least one of the units, a second control signal for varying a power supply potential supplied to at least one of the units, and a third control signal for stopping supplying a clock signal to at least one of the units,

wherein the central processing unit includes a plurality of elements, and

wherein the antenna is provided over a substrate on which the plurality of elements are formed.

5. The semiconductor device according to any one of claims 1 to 4, further comprising a glass substrate,

wherein the plurality of units and the control circuit are provided over the glass substrate.

6. The semiconductor device according to any one of claims 1 to 4, further comprising a flexible substrate,

wherein the plurality of units and the control circuit are provided over the flexible substrate.

7. The semiconductor device according to any one of claims 1 to 4,

wherein the plurality of units are selected from a bus interface, a data cache, an instruction decoder, a reservation station, an instruction cache, an arithmetic logical unit, a floating point unit, a branch unit, a load/store unit, and a general purpose register.

8. The semiconductor device according to any one of claims 1 to 4,

wherein the plurality of units are selected from a pipeline unit, a peripheral memory controller, and a peripheral bus controller.

2. A semiconductor device comprising:

a central processing unit including a plurality of units and a control circuit;

an antenna;

a power supply circuit;

a clock generation circuit;

a plurality of first switches provided between the plurality of units and the power supply circuit, wherein each of the plurality of first switches corresponds to one of the plurality of units; and

a plurality of second switches provided between the plurality of units and the clock generation circuit, wherein each of the plurality of second switches corresponds to one of the plurality of units,

wherein the control circuit outputs to at least one of the first switches and the second switches, based on a power supply signal including data on power supply from the antenna, at least one of a first control signal for stopping power supply to at least one of the units, a second control signal for varying a power supply potential supplied to at least one of the units, and a third control signal for stopping supplying a clock signal to at least one of the units,

wherein the central processing unit includes a plurality of elements, and

wherein the antenna is provided over a substrate on which the plurality of elements are formed.

3. A semiconductor device comprising:

a central processing unit including a plurality of units and a control circuit;

an antenna;

a power supply circuit; and

a clock generation circuit,

wherein the control circuit outputs to at least one of the power supply circuit and the clock generation circuit, based on a load signal obtained by an event signal supplied from each of the units, at least one of a first control signal for stopping power supply to at least one of the units, a second control signal for varying a power supply potential supplied to at least one of the units, and a third control signal for stopping supplying a clock signal to at least one of the units,

wherein the central processing unit includes a plurality of elements, and

wherein the antenna is provided over a substrate on which the plurality of elements are formed.

4. A semiconductor device comprising:

a central processing unit including a plurality of units and a control circuit;

an antenna;

a power supply circuit;

a clock generation circuit;

a plurality of first switches provided between the plurality of units and the power supply circuit, wherein each of the plurality of first switches corresponds to one of the plurality of units; and

a plurality of second switches provided between the plurality of units and the clock generation circuit, wherein each of the plurality of second switches corresponds to one of the plurality of units,

wherein the control circuit outputs to at least one of the first switches and the second switches, based on a load signal obtained by an event signal supplied from each of the units, at least one of a first control signal for stopping power supply to at least one of the units, a second control signal for varying a power supply potential supplied to at least one of the units, and a third control signal for stopping supplying a clock signal to at least one of the units,

wherein the central processing unit includes a plurality of elements, and

wherein the antenna is provided over a substrate on which the plurality of elements are formed.