System and method for efficient uncorrectable error detection in flash memory

• US 7,707,481 B2
• Filed: 05/16/2006
• Issued: 04/27/2010
• Est. Priority Date: 05/16/2006
• Status: Expired due to Fees

• Current Assignee: Pitney Bowes Incorporated (Böwe Systec AG)
• Original Assignee: Pitney Bowes Incorporated (Böwe Systec AG)
• Inventors: Jacobson, Gary S., Kirschner, Wesley A., Hurd, John A., Sisson, Robert W.
• Primary Examiner(s): Chaudry; M. Mujtaba K
• Assistant Examiner(s): Ahmed; Enam
• Application Number:
  US11/436,171
• Publication Number:
  US 20070283224A1
• Time in Patent Office: 1,442 Days
• Field of Search: 714/763, 714/1, 714/41, 714/6, 714/758, 714/768
• US Class Current: 714/763
• CPC Class Codes: G06F 11/1012 using codes or arrangements adapted for a specific type of error G06F11/1048 takes precedence

Abstract

A system and method for efficient uncorrectable error detection in flash memory is described. A microcontroller including a non-volatile flash memory utilizes an Error Correction Code (ECC) having a certain error detection and correction bit strength. The user data is first processed by a hash function and hash data is stored with the user data. Then, the user data and hash data are processed by the ECC system. In detection, the hash ensures that a relatively low bit-strength ECC system did not incorrectly manipulate the user data. Such a hash integrity check provides an efficient, robust detection of incorrectly corrected user data resulting from errors beyond the correction but strength of the ECC system utilized.

Claims

1. A method of increasing data reliability of a memory device comprising:

applying a first error process to a user data block resulting in first error process data;

applying a second error process to the user data block and the first error process data resulting in second error process data;

storing the user data block, the first error process data and the second error process data to the memory device as a data block.

2. The method according to claim 1 wherein the memory device is a flash memory device.

3. The method according to claim 2 wherein the first error process is a hash process and the first error process data includes hash data.

4. The method according to claim 3 wherein the first error process is a SHA-1 hash process that is applied to the entire user block.

5. The method according to claim 2 wherein the second error process is an Error Correction Code (ECC) process.

6. The method according to claim 5 wherein the ECC process is applied to subgroups of the user data block including appended hash data.

7. The method according to claim 6 wherein the ECC process utilizes a (38, 32) Hamming code.

8. The method according to claim 4 wherein the hash data is a subset of the output of the SHA-1 hash process.

9. A method of increasing data reliability of a memory device by detecting uncorrectable errors in the memory device utilizing a first error process resulting in a first error process data and a second error process resulting in a second error process data comprising:

obtaining a raw data block from the memory device including user data, first error process data and second error process data, wherein the second error process data was generated based upon the user data and the first error process data;

determining if the second error process data is consistent with the user data and the first error process data by utilizing the second error process;

if the second error process data is not consistent with the user data and the first error process data, utilizing the second error process to generate corrected user data and corrected first error process data;

determining if the corrected first error process data is consistent with the corrected user data by utilizing the first error process;

if the corrected first error process data is not consistent with the corrected user data, then indicating a failure and halting operation; and

if the corrected first error process data is consistent with the corrected user data, then outputting the corrected user data.

10. The method according to claim 9 wherein the memory device is a flash memory device.

11. The method according to claim 10 wherein the first error process is a hash process and the first error process data includes hash data.

12. The method according to claim 11 wherein the first error process is a SHA-1 hash process and wherein the hash data is a subset of the output of the SHA-1 hash process.

13. The method according to claim 10 wherein the second error process is an Error Correction Code (ECC) process.

14. The method according to claim 13 wherein the ECC process is applied to subsets of the user data block.

15. The method according to claim 14 wherein the ECC process utilizes a (38, 32) Hamming code.

16. The method according to claim 9 further comprising:

if the corrected first error process data is not consistent with the corrected user data, sending the flash memory data contents to another device before halting operation.

17. A postage printing system achieving increased data reliability comprising:

a memory device; and

a controller coupled to the memory device, the controller configured to include;

means for obtaining a raw data block from the memory device including user data, first error process data and second error process data, wherein the second error process data was generated based upon the user data and the first error process data;

means for determining if the second error process data is consistent with the user data and the first error process data by utilizing the second error process;

means for utilizing the second error process to generate corrected user data and corrected first error process data if the second error process data is not consistent with the user data and the first error process data;

means for determining if the corrected first error process data is consistent with the corrected user data by utilizing the first error process;

means for indicating a failure and halting operation if the corrected first error process data is not consistent with the corrected user data; and

means for outputting the corrected user data if the corrected first error process data is consistent with the corrected user data.

18. The system according to claim 17 wherein the memory device is a flash memory device.

19. The system according to claim 18 wherein,

the first error process is a SHA-1 hash process and the first error process data includes hash data;

the second error process is an Error Correction Code (ECC) process that is applied to subsets of the user data block and that utilizes a (38,

     32) Hamming code; and

the hash data is a subset of the output of the SHA-1 hash process.

20. The system according to claim 18 wherein the controller is further configured to include:

means for sending the flash memory contents to another device if the corrected first error process data is not consistent with the corrected user data.