System and method for performing verification based upon both rules and models

• US 7,707,528 B1
• Filed: 02/24/2007
• Issued: 04/27/2010
• Est. Priority Date: 02/24/2007
• Status: Expired due to Fees

• Current Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Original Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Inventors: Koshy, Mathew, White, David, Ruehl, Roland
• Primary Examiner(s): GARBOWSKI, LEIGH M
• Application Number:
  US11/678,592
• Time in Patent Office: 1,158 Days
• Field of Search: None
• US Class Current: 716/106
• CPC Class Codes: G03F 1/36 Masks having proximity correction features; Preparation thereof, e.g. optical proximity correction [OPC] design processes
• CPC Class Codes: G06F 2119/18 Manufacturability analysis or optimisation for manufacturability
• CPC Class Codes: G06F 30/367 Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36
• CPC Class Codes: Y02P 90/02 Total factory control, e.g. smart factories, flexible manufacturing systems [FMS] or integrated manufacturing systems [IMS]

Abstract

Methods and systems for integrating both models and rules into a verification flow to address both of these issues. Models are employed to perform simulations to provide more accurate verification results. In addition, the lithography simulation results can be used to fine-tune the rules themselves to provide a more realistic check upon circuit designs.

Claims

1. A computer-implemented method for performing verification comprising:

predicting the physical realization of a layout design based at least in part upon model parameters;

analyzing the predicted layout design using model-based design rules, wherein the model-based design rules are associated with a model-based buffer distance smaller than a design rule check (DRC) buffer distance used with a DRC rule;

determining areas of violation based at least in part upon the analyzed layout design, wherein the act of determining areas of violation comprises using a processor; and

storing the areas in a volatile or non-volatile computer-usable medium or displaying the areas on a display device.

2. The method of claim 1, wherein the physical realization is predicted by systematic modeling comprising parametric and functional characteristics and yield.

3. The method of claim 2, further comprising calculating as-manufactured-product features utilizing information of the fabrication process and interaction of the materials.

4. The method of claim 3, wherein the information comprises manufacturing information and design intent rules.

5. The method of claim 1, wherein the layout design is divided into sections for distributed processing.

6. The method of claim 1, wherein predicting the physical realization comprises customization of certain design types.

7. The method of claim 1, wherein predicting the physical realization comprises simulating using models and design for manufacturing (DFM) information.

8. The method of claim 1, wherein the layout space used for the predicted layout design has a more compact design layout due to the smaller model-based buffer distance for a desired manufactured yield than if the layout space uses DRC rules having the desired manufactured yield.

9. A system for performing verification comprising:

means for predicting a physical realization of a layout design based at least in part upon model parameters;

means for analyzing the predicted layout design model-based design rules, wherein the model-based design rules are associated with a model-based buffer distance smaller than a design rule check (DRC) buffer distance used with a DRC rule;

a processor for determining areas of violation based at least in part upon the analyzed layout design; and

a volatile or non-volatile computer-usable medium for storing the areas or a display device for displaying the areas.

10. The system of claim 9, wherein the physical realization is predicted by systematic modeling comprising parametric and functional characteristics and yield.

11. The system of claim 10, further comprising means for calculating as-manufactured-product features utilizing information of the fabrication process and interaction of the materials.

12. The system of claim 11, wherein the information comprises manufacturing information and design intent rules.

13. The system of claim 9, wherein the layout design is divided into sections for distributed processing.

14. The system of claim 9, wherein means for predicting the physical realization comprises customization of certain design types.

15. The system of claim 9, wherein means for predicting the physical realization comprises simulating using models and design for manufacturing (DFM) information.

16. The system of claim 9, wherein the layout space used for the predicted layout design has a more compact design layout due to the smaller model-based buffer distance for a desired manufactured yield than if the layout space uses DRC rules having the desired manufactured yield.

17. A computer program product embodied in a volatile or non-volatile computer-usable medium, storing executable code to execute a process for performing verification, the process comprising:

predicting the physical realization of a layout design based at least in part upon model parameters;

analyzing the predicted layout design using model-based design rules, wherein the model-based design rules are associated with a model-based buffer distance smaller than a design rule check (DRC) buffer distance used with a DRC rule; and

determining areas of violation based at least in part upon the analyzed layout design; and

storing the areas or displaying the areas on a display device.

18. The product of claim 17, wherein the physical realization is predicted by systematic modeling comprising parametric and functional characteristics and yield.

19. The product of claim 18, further comprising calculating as-manufactured-product features utilizing information of the fabrication process and interaction of the materials.

20. The product of claim 19, wherein the information comprises manufacturing information and design intent rules.

21. The product of claim 17, wherein the layout design is divided into sections for distributed processing.

22. The product of claim 17, wherein predicting the physical realization comprises simulating using models and design for manufacturing (DFM) information.

23. The product of claim 17, wherein the layout space used for the predicted layout design has a more compact design layout due to the smaller model-based buffer distance for a desired manufactured yield than if the layout space uses DRC rules having the desired manufactured yield.