Dual mode tuner for co-existing digital and analog television signals

• US 7,707,617 B2
• Filed: 06/11/2003
• Issued: 04/27/2010
• Est. Priority Date: 08/01/1997
• Status: Active Grant

• Current Assignee: CSR Technology Incorporated (Qualcomm, Inc.)
• Original Assignee: Microtune, Inc. (Qualcomm, Inc.)
• Inventors: Birleson, Vince
• Primary Examiner(s): Kelley; Christopher
• Assistant Examiner(s): BROWN, RUEBEN M
• Application Number:
  US10/459,125
• Publication Number:
  US 20040004674A1
• Time in Patent Office: 2,512 Days
• Field of Search: 348/731, 455/3.2, 455/22, 455/143, 455/189.1, 455/259, 455/265, 331/22, 331/32, 725/151, 725/100
• US Class Current: 725/151
• CPC Class Codes: H03D 2200/0025 Gain control circuits
• CPC Class Codes: H03D 2200/009 Reduction of local oscillator or RF leakage
• CPC Class Codes: H03D 7/1433 using bipolar transistors H03D7/145 takes precedence
• CPC Class Codes: H03D 7/1458 Double balanced arrangements, i.e. where both input signals are differential
• CPC Class Codes: H03D 7/1491 Arrangements to linearise a transconductance stage of a mixer arrangement
• CPC Class Codes: H03D 7/161 all the frequency changers being connected in cascade
• CPC Class Codes: H03L 7/23 with pulse counters or frequency dividers
• CPC Class Codes: H04N 21/426 Internal components of the client ; Characteristics thereof H04N5/44 takes precedence
• CPC Class Codes: H04N 21/42638 involving a hybrid front-end, e.g. analog and digital tuners
• CPC Class Codes: H04N 5/46 for receiving on more than one standard at will deflecting circuits of multi-standard receivers H04N3/27
• CPC Class Codes: H04N 5/50 Tuning indicators; Automatic tuning control

Abstract

A dual mode tuner/receiver is disclosed in which both analog and digital signals can be received and processed. A low pass filter allows all channels below a selected frequency enter the circuit. A precisely controlled dual conversion circuit creates an intermediate frequency (IF) signal. An automatic carrier detection circuit monitors the IF signal and determines whether the signal is of analog or digital format and intermediate frequency filters are adjusted based upon the type of signal detected. A coherent oscillator circuit generates in-phase and quadrature reference signals that are used by video and audio detectors for further processing of the IF signal. In-phase and quadrature outputs are provided for digital signals and composite video and audio outputs are provided for analog signals.

Claims

1. A tuner for receiving analog and digital television signals comprising:

an input filter receiving an RF signal having a plurality of channels and removing frequencies in said RF signal above an input cutoff frequency;

a first mixer having a first input coupled to said input filter and a second input coupled to a first reference signal, wherein said first mixer generates a first IF signal;

a first IF filter coupled to said first mixer and filtering said first IF signal;

a second mixer having a first input coupled to said first IF filter and a second input coupled to a second reference signal, wherein said second mixer generates a second IF signal;

a second IF filter coupled to said second mixer and having a band pass characteristic suitable for passing a first signal format to generate a third IF signal;

a switch coupled to said second IF filter and operating to selectively direct said third IF signal either to a third IF filter or to an attenuator to generate a fourth IF signal, wherein a combination of said third IF filter and said second IF filter has a band pass characteristic suitable for passing a second signal format;

a coherent oscillator coupled to the output of said switch and generating a first phase reference signal and a second phase reference signal from said fourth IF signal;

a first detector having a first input receiving said fourth IF signal and a second input receiving said first phase reference signal; and

a second detector having a first input receiving said fourth IF signal and a second input receiving said second phase reference signal.

2. The tuner of claim 1 constructed substantially on a single integrated circuit substrate.

3. The tuner of claim 1 further comprising:

a format detector monitoring the output of said second IF filter and said third IF filter to determine whether a selected channel is a first signal format or a second signal format.

4. The tuner of claim 1 wherein said first IF filter, said second IF filter and said third IF filter are discrete elements and the remainder of the tuner is constructed on a single integrated circuit substrate.

5. The tuner of claim 1 wherein said fourth IF signal is provided to a separate decoder for further signal processing.

6. The tuner of claim 1 further comprising:

a delayed gain amplifier having an input coupled to said input filter and an output coupled to said first mixer;

an IF gain amplifier coupled to said switch; and

a gain control circuit coupled to said IF gain amplifier;

wherein said gain control circuit adjusts the gain of said IF amplifier and said delayed gain amplifier to control the signal level in said tuner.

7. The tuner of claim 1 further comprising:

frequency discriminator coupled to said coherent oscillator and monitoring an operating frequency of said coherent oscillator.

8. The tuner of claim 1 further comprising:

a first low pass filter coupled to an output of said first detector;

a first output buffer coupled to said first low pass filter;

a second low pass filter coupled to an output of said second detector; and

a second output buffer coupled to said second low pass filter;

wherein a selected one of said channels is in a digital television format and a digital in-phase signal is output at said first output buffer.

9. The tuner of claim 8 wherein a digital quadrature signal is output at said second output buffer.

10. The tuner of claim 8 further comprising:

a first analog-to-digital converter coupled between said first low pass filter and said first output buffer; and

a second analog-to-digital converter coupled between said second low pass filter and said second output buffer.

11. The tuner of claim 10 constructed substantially on a single integrated circuit substrate.

12. The tuner of claim 11, wherein said first and second analog-to-digital converters are not physically located on said single integrated circuit substrate.

13. The tuner of claim 8 wherein said first IF filter, said second IF filter and said third IF filter are discrete elements and the remainder of said tuner is constructed on a single integrated circuit substrate.

14. The tuner of claim 8 constructed substantially on a single integrated circuit substrate.

15. The tuner of claim 14, wherein said first and second low pass filters are not physically located on said single integrated circuit substrate.

16. The tuner of claim 1 further comprising:

a sound trap filter coupled to an output of said first detector;

a noise clipping circuit coupled to said sound trap filter;

a first output buffer coupled to said noise clipping circuit;

a chroma reject filter coupled to an output of said second detector;

a third mixer having a first input coupled to said chroma reject filter and a second filter coupled to a third reference signal;

a sound filter coupled to an output of said third mixer;

an FM demodulator coupled to said sound filter; and

a second output buffer coupled to said FM demodulator;

wherein a selected one of said channels is in an analog television format and a composite video signal is output at said first output buffer and a composite audio signal is output at said second output buffer.

17. The tuner of claim 16 wherein said first IF filter, said second IF filter and said third IF filter are discrete elements and the remainder of said tuner is constructed on a single integrated circuit substrate.

18. The tuner of claim 16 constructed substantially on a single integrated circuit substrate.

19. The tuner of claim 18, wherein said sound trap filter and said sound filter are not physically located on said single integrated circuit substrate.

20. The tuner of claim 16, wherein all of said filters are not physically located on said single integrated circuit substrate.

21. The tuner of claim 1, further comprising a frequency synthesizer for generating said first and second reference signals.

22. The tuner of claim 21, wherein a crystal connected to an oscillator circuit provides a signal to said frequency synthesizer for generating said first and second reference signals.

23. The tuner of claim 22 constructed substantially on a single integrated circuit substrate.

24. The tuner of claim 23, wherein said crystal is not physically located on said single integrated circuit substrate.

25. The tuner of claim 24, wherein said crystal is a 5.25 MHz crystal.

26. A circuit comprising:

means for converting a received signal from RF to IF;

a first filter for filtering said IF signal;

a second filter for filtering said IF signal;

means for detecting the amplitude of the IF signal from said first filter and the IF signal from said second filter;

means for establishing a difference between said detected amplitude levels; and

means for comparing said established differences against pre-established reference levels for determining signal formats when those signal formats arrive in RF form.

27. The circuit of claim 26 wherein said first and second filters are in series.

28. The circuit of claim 27 wherein said first filter matches a first format.

29. The circuit of claim 27 wherein a combination of said first and second filters matches a second format.

30. The circuit of claim 26 wherein said comparing means provides control for either digital, analog or analog suppressed carrier formats.

31. The circuit of claim 26 wherein said first and second filters are in parallel.

32. The circuit of claim 31 wherein said first filter matches a first format and second filter matches a second format.

33. The circuit of claim 26 constructed substantially on a single integrated circuit substrate.

34. The circuit of claim 33, wherein said first and second filters are not physically located on said single integrated circuit substrate.