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Stacked non-volatile memory device and methods for fabricating the same

  • US 7,709,334 B2
  • Filed: 06/22/2006
  • Issued: 05/04/2010
  • Est. Priority Date: 12/09/2005
  • Status: Active Grant
First Claim
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1. A method for fabricating a non-volatile memory device comprising a plurality of bit line layers and a plurality of word line layers sequentially formed on top of each other, the method comprising:

  • forming a first bit line layer, wherein forming the first bit line layer comprises;

    forming a semiconductor layer on an insulator;

    patterning the semiconductor layer to form a plurality of bit lines;

    forming a first word line layer over the first bit line layer, wherein forming the first word line layer comprises;

    sequentially forming a first storage structure, a conducting layer and a second storage structure; and

    after said sequentially forming, patterning the first and second storage structures and the conducting layer to form a plurality of word lines to define memory cells including channel regions in the bit lines of the plurality of bit lines arranged in a NAND-type array.

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