Stacked non-volatile memory device and methods for fabricating the same

• US 7,709,334 B2
• Filed: 06/22/2006
• Issued: 05/04/2010
• Est. Priority Date: 12/09/2005
• Status: Active Grant

• Current Assignee: Macronix International Co., Ltd.
• Original Assignee: Macronix International Co., Ltd.
• Inventors: Lai, Erh-Kun, Hsieh, Kuang-Yeu, Lue, Hang-Ting
• Primary Examiner(s): Pham; Thanh V
• Assistant Examiner(s): Ligai; Maria
• Application Number:
  US11/425,959
• Publication Number:
  US 20070134855A1
• Time in Patent Office: 1,412 Days
• Field of Search: 257/E29.316, 257/E29.126, 257/314, 438/142, 438/287, 438/197, 438/261
• US Class Current: 438/287
• CPC Class Codes: H01L 21/8221 Three dimensional integrated circuits stacked in different levels
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/40117 the electrodes comprising a charge-trapping insulator
• CPC Class Codes: H01L 29/792 with charge trapping gate insulator, e.g. MNOS-memory transistors
• CPC Class Codes: H10B 43/10 characterised by the top-view layout
• CPC Class Codes: H10B 43/20 characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 43/30 characterised by the memory core region
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A stacked non-volatile memory device comprises a plurality of bit line and word line layers stacked on top of each other. The bit line layers comprise a plurality of bit lines that can be formed using advanced processing techniques making fabrication of the device efficient and cost effective. The device can be configured for NAND operation.

Claims

1. A method for fabricating a non-volatile memory device comprising a plurality of bit line layers and a plurality of word line layers sequentially formed on top of each other, the method comprising:

forming a first bit line layer, wherein forming the first bit line layer comprises;

forming a semiconductor layer on an insulator;

patterning the semiconductor layer to form a plurality of bit lines;

forming a first word line layer over the first bit line layer, wherein forming the first word line layer comprises;

sequentially forming a first storage structure, a conducting layer and a second storage structure; and

after said sequentially forming, patterning the first and second storage structures and the conducting layer to form a plurality of word lines to define memory cells including channel regions in the bit lines of the plurality of bit lines arranged in a NAND-type array.

2. The method of claim 1, wherein patterning and etching the semiconductor layer comprises:

forming a cap layer over the semiconductor layer;

etching the cap layer and the semiconductor layer to form bit line regions comprising remaining portions of the cap layer and the semiconductor layer;

forming a dielectric layer over the etched cap and semiconductor layers;

etching a portion of the dielectric layer to form dielectric regions between the bit line regions and on top of the remaining portions of the cap layer; and

removing the remaining portions of the cap layer thereby removing the portions of the dielectric layer on top of the cap layer.

3. The method of claim 2, wherein the cap layer comprises a nitride layer.

4. The method of claim 2, wherein the dielectric layer comprises silicon dioxide.

5. The method of claim 4, wherein the silicon dioxide is deposited using high density plasma, chemical vapor deposition.

6. The method of claim 1, wherein forming each of the first and second storage structures comprises forming a silicon-oxide-nitride-oxide-silicon (SONOS) structure.

7. The method of claim 1, wherein forming each of the first and second storage structures comprises forming an oxide-nitride-oxide (ONO), nitride read only memory structure.

8. The method of claim 1, wherein forming each of the first and second storage structures comprises forming a silicon-oxide-nitride-silicon (SONS) structure.

9. The method of claim 1, wherein forming each of the first and second storage structures comprises forming a top silicon-oxide-nitride-silicon (SONOSOS) structure.

10. The method of claim 1, wherein forming each of the first and second storage structures comprises forming a bottom silicon-oxide-silicon-oxide-nitride-oxide-silicon (SOSONOS) structure.

11. The method of claim 1, wherein forming each of the first and second storage structures comprises forming a silicon-oxide-nitride-oxide-nitride-silicon (SONONS) structure.

12. The method of claim 1, wherein forming each of the first and second trapping structures comprises forming a silicon nitride (SiN) layer.

13. The method of claim 1, wherein forming each of the first and second storage structures comprises forming a SiON layer.

14. The method of claim 1, wherein forming each of the first and second storage structures comprises depositing a Hi-K material.

15. The method of claim 14, wherein the Hi-K material is HfO₂, AIN, or Al₂O₃.

16. The method of claim 1, further comprising forming source/drain regions in the regions of the plurality of bit lines not covered by the plurality of word lines.

17. The method of claim 16, wherein the semiconductor layer comprises a P-type semiconductor material, and wherein forming the source/drain regions comprises forming N+ regions in the P-type semiconductor material.

18. The method of claim 17, wherein the N+ regions are formed using As or P.

19. The method of claim 16, wherein:

bit lines in the plurality of bit lines are spaced apart along a first direction; and

the source/drain regions of respective memory cells are spaced apart in a corresponding bit line in the plurality of bit lines along a second direction transverse to the first direction.

20. The method of claim 19, wherein adjacent memory cells share a source/drain region.

21. The method of claim 1, wherein the conducting layer comprises polysilicon material.

22. The method of claim 21, wherein the conducting layer comprises polysilicon/silicide/polysilicon material.

23. The method of claim 21, wherein the conducting layer comprises a metal.

24. The method of claim 23, wherein the metal is aluminum, copper, or tungsten.

25. The method of claim 1, further comprising forming a second bit line layer over the first word line layer.

26. The method of claim 25, further comprising forming a second word line layer over the second bit line layer.

27. The method of claim 1, wherein:

bit lines in the plurality of bit lines have a bit line width, and adjacent bit lines in the plurality of bit lines are spaced apart along a first direction by a bit line separation distance;

word lines in the plurality of word lines have a word line width, and adjacent word lines in the plurality of word lines are spaced apart along a second direction by a word line separation distance; and

the memory cells have an area, the area having a first side along the first direction and a second side along the second direction, the first side having a length equal to a sum of the bit line width and the bit line separation distance, the second side having a length equal to a sum of the word line width and the word line separation distance.

28. A method for fabricating a memory device comprising:

forming a first plurality of semiconductor bit lines;

forming a first multi-layer storage structure on the first plurality of semiconductor bit lines, forming word line material on the first multi-layer storage structure, and forming a second multi-layer storage structure on the word line material;

patterning the first multi-layer storage structure, the word line material and the second multi-layer storage structure to expose portions of the first plurality of semiconductor bit lines, thereby forming a plurality of word lines comprising word line material;

forming a first plurality of doped regions within the exposed portions of the first plurality of semiconductor bit lines, the first plurality of doped regions having a conductivity type different from that of the first plurality of semiconductor bit lines, wherein memory cells in a first plurality of memory cells include a portion of the first multi-layer storage structure between a corresponding word line in the plurality of word lines and a channel region separated by a pair of doped regions in the first plurality of doped regions in a corresponding semiconductor bit line in the first plurality of semiconductor bit lines;

forming a second plurality of semiconductor bit lines on the second storage structure; and

forming a second plurality of doped regions within the second plurality of semiconductor bit lines, the second plurality of doped regions having a conductivity type different from that of the second plurality of semiconductor bit lines, wherein memory cells in a second plurality of memory cells include a portion of the second storage structure between a corresponding word line in the plurality of word lines and a channel region separated by a pair of doped regions in the second plurality of doped regions in a corresponding semiconductor bit line in the second plurality of semiconductor bit lines.