Semiconductor component and method

• US 7,709,887 B2
• Filed: 11/28/2006
• Issued: 05/04/2010
• Est. Priority Date: 11/28/2005
• Status: Active Grant

• Current Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Original Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Inventors: Hille, Frank, Pfaffenlehner, Manfred, Laska, Thomas, Umbach, Frank, Schulze, Hans-Joachim, Mauder, Anton
• Primary Examiner(s): Quach; Tuan N.
• Application Number:
  US11/604,984
• Publication Number:
  US 20070152268A1
• Time in Patent Office: 1,253 Days
• Field of Search: 257/330, 257/334, 257/E29.197, 257/E29.2, 257/E29.201, 257/329, 257/331, 257/333
• US Class Current: 257/330
• CPC Class Codes: H01L 21/263 with high-energy radiation H01L21/261 takes precedence
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/66348 with a recessed gate
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT

Abstract

A semiconductor component and method of making a semiconductor component is disclosed. In one embodiment, the semiconductor component includes a drift region of a first conductivity type, a body region of a second conductivity type, and a trench extending into the body region. A semiconductor region of the first conductivity type is in contact with the drift region and the body region and is arranged at a distance from the trench.

Claims

1. An insulated gate semiconductor component comprising:

a first semiconductor region comprising drift region of a first conductivity type;

a second semiconductor region comprising body region of a second conductivity type, formed on or in an upper main surface of the first semiconductor region, said second conductivity type being opposite to said first conductivity type;

a third semiconductor region comprising an emitter region of the first conductivity type formed selectively in a front surface of the second semiconductor region;

a trench having an opening in the front surface of the third semiconductor region and extending into a depth from the opening into the second semiconductor region;

a dielectric layer provided in the trench and completely covers a bottom thereof and extends to a location higher than an upper main surface of the first semiconductor region;

a gate electrode filled in the interior of the trench; and

a fourth semiconductor region of the first conductivity type in direct contact with the first and second semiconductor regions, wherein the fourth semiconductor region is arranged at a distance from the trench,

wherein a distance between the trench and the fourth semiconductor region is within the range of 10-200 nm, and

wherein a dopant dose of the fourth semiconductor region is within the range of 1×

10¹¹ cm<sup>−

2</sup> to 1×

10¹² cm<sup>−

2</sup>.

2. The semiconductor component as claimed in claim 1, comprising wherein the second semiconductor region has a contact layer more heavily doped with the dopants of the second conductivity type than the second semiconductor region.

3. The semiconductor component as claimed in claim 1, comprising wherein the distance between the trench and the fourth semiconductor region is within the range of 50-150 nm.

4. The semiconductor component as claimed in claim 1, comprising wherein the distance between the trench and the fourth semiconductor region is within the range of 100-120 nm.

5. The semiconductor component as claimed in claim 1, comprising wherein a penetration depth of the fourth semiconductor region does not exceed twice a penetration depth of the trench.

6. The semiconductor component as claimed in claim 1, comprising wherein a penetration depth of the trench is within the range of 4 μ

m to 8 μ

m.

7. The semiconductor component as claimed in claim 6, comprising wherein a penetration depth of the fourth semiconductor region is within the range of 3 μ

m to 16 μ

m.

8. The semiconductor component as claimed in claim 7, comprising wherein a penetration depth of the fourth semiconductor region is within the range of 3 μ

m to 10 μ

m.

9. The semiconductor component as claimed in claim 1, comprising wherein the fourth semiconductor region is doped with a dose that is lower than the breakdown charge.

10. The semiconductor component as claimed in claim 1, comprising wherein the fourth semiconductor region is doped with a dose that is 1-70% of the breakdown charge.

11. The semiconductor component as claimed in claim 1, comprising wherein a layer of the first conductivity type is arranged as a field stop layer below the first semiconductor region of a first conductivity type, said layer being more highly doped than the first semiconductor region.

12. The semiconductor component as claimed in claim 11, comprising wherein the field stop layer has a doping within the range of 1×

10¹⁴ to 5×

10¹⁴ charge carriers cm<sup>−

3</sup>.

13. The semiconductor component as claimed in claim 1, comprising wherein a layer of the second conductivity type is arranged as a collector layer, at a lower main area of the semiconductor component.

14. The semiconductor component as claimed in claim 1, comprising wherein an edge structure of the semiconductor component has a high blocking capability.

15. The semiconductor component as claimed in claim 1, comprising wherein an edge structure is a VLD structure.

16. The semiconductor component as claimed in claim 1, comprising wherein a charge carrier lifetime is reduced in an edge region of the semiconductor component by a recombination zone formed by a masked electron irradiation.

17. The semiconductor component as claimed in claim 16, comprising wherein, in a vertical direction of the component, the charge carrier lifetime is reduced in a p-type emitter layer or shortly before the latter, but in total over not more than ⅕

of the vertical component extent.

18. The semiconductor component as claimed in claim 17, comprising wherein the charge carrier lifetime is limited in regions below an edge of the semiconductor component which regions extend up to a maximum of five ambipolar diffusion lengths from the edge into the cell array.

19. The semiconductor component as claimed in claim 18, comprising wherein the charge carrier lifetime is limited by proton or helium irradiation.

20. The semiconductor component as claimed in claim 1, comprising wherein a chip rear side of the semiconductor component is treated by a proton or helium irradiation prior to the production of a rear side emitter of the semiconductor component.

21. The semiconductor component as claimed in claim 16, comprising wherein a collector layer of the semiconductor component is not present in an edge region of the semiconductor component.