Semiconductor wafer having a separation portion on a peripheral area

• US 7,709,932 B2
• Filed: 10/07/2005
• Issued: 05/04/2010
• Est. Priority Date: 07/01/2003
• Status: Active Grant

• Current Assignee: Kioxia Corporation
• Original Assignee: Renesas Technology Corporation (Renesas Electronics Corporation)
• Inventors: Nemoto, Yoshihiko, Takahashi, Kenji, Sunohara, Masahiro
• Primary Examiner(s): Smith; Zandra
• Assistant Examiner(s): Duong; Khanh B.
• Application Number:
  US11/245,059
• Publication Number:
  US 20060038260A1
• Time in Patent Office: 1,670 Days
• Field of Search: None
• US Class Current: 257/618
• CPC Class Codes: H01L 21/3043 Making grooves, e.g. cutting
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 21/6836 Wafer tapes, e.g. grinding or dicing support tapes adhesive tapes in general C09J7/20
• CPC Class Codes: H01L 21/78 with subsequent division of the substrate into plural individual devices cutting to change the surface-physical characteristics or shape of semiconductor bodies H01L21/304
• CPC Class Codes: H01L 2221/68327 used during dicing or grinding
• CPC Class Codes: H01L 2221/6834 used to protect an active side of a device or wafer
• CPC Class Codes: H01L 2221/68363 used in a transfer process involving transfer directly from an origin substrate to a target substrate without use of an intermediate handle substrate
• CPC Class Codes: H01L 29/0657 characterised by the shape of the body
• CPC Class Codes: Y02E 10/52 PV systems with concentrators
• CPC Class Codes: Y10S 438/977 Thinning or removal of substrate

Abstract

A conveyance system for a semiconductor wafer can be used without any change before and after a support plate is adhered to the wafer. Also, the finish accuracy of the wafer and the positioning accuracy between the wafer and the support plate can be relaxed, thus improving the manufacturing efficiency. The wafer is formed on its peripheral portion with a stepped portion, which is deeper than a finished thickness obtained by partial removal of the rear surface thereof and which can be eliminated by the partial removal of the wafer rear surface. The separation portion has a length which extends radially outward from a flat surface, and which is greater than a total sum of a maximum-minimum difference between the finish allowances of the diameters of the wafer and the support plate, and a maximum value of a positioning error between the wafer and the support plate generated upon adhesion thereof.

Claims

1. A semiconductor wafer comprising:

a front surface and an opposing rear surface,

the front surface comprising a flat central portion and

a peripheral portion surrounding the flat central portion, wherein

a semiconductor circuit is formed in the flat central potion and

the peripheral portion comprises a stepped portion having vertical surface formed at an outer edge of the flat central portion, a front surface of the stepped portion formed horizontally to the vertical surface, an annular groove formed in the horizontally formed front surface at the vertical surface, and a chamfer formed where the vertical surface and the flat central portion meet.