Controller for the three-phase cascade multilevel converter used as shunt active filter in unbalanced operation with guaranteed capacitors voltages balance

US 7,710,082 B2
Filed: 10/18/2007
Issued: 05/04/2010
Est. Priority Date: 10/18/2007
Status: Expired due to Fees

First Claim

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1. A controller providing a control vector to a cascade H-bridge three-phase multilevel converter used as a shunt active filter, each phase of the multilevel converter composed of a series connection of two H-bridge cells, each of said phases of the multilevel converter providing a five-level voltage signal, each of said H-bridge cells composed of an H-bridge inverter having an output capacitor and an output resistor coupled across the said H-bridge, each of said H-bridge cells providing an output voltage, each of said phases of the multilevel converter coupled to a corresponding phase of a three-phase power distribution system via a corresponding inductor, each of said phases of the multilevel converter providing an injected current across the corresponding inductor, the said three phases of the multilevel converter connected among them in a star connection, the three phase power distribution system providing a source voltage and a source current for each phase to a corresponding three phase load, the controller comprising:

a source current module operative to provide a signal indicative of the value of the source current in each phase;

a source voltage module operative to provide a signal indicative of the value of the source voltage in each phase;

an output voltage module operative to provide a signal indicative of the output voltage across the output capacitor of each H-bridge cell;

a three-phase to stationary coordinate converter operative to convert the measured three-phase source current value into a source current value and to convert the three-phase source voltage value into a source voltage value in stationary coordinates;

a voltages transformation processor 1 coupled to the output voltage module and receiving the output voltages across a first pair of output capacitors, the transformation processor 1 configured and arranged to provide variables z₁and y₁;

a voltages transformation processor 2 coupled to the output voltage module and receiving the output voltages across a second pair of output capacitors, the transformation processor 1 configured and arranged to provide variables z₂and y₂;

a voltages transformation processor 3 coupled to the output voltage module and receiving the output voltages across a third pair of output capacitors, the transformation processor 1 configured and arranged to provide variables z₃and y₃;

a coordinates transformation processor coupled to voltages transformation processors 1, 2 and 3, and receiving variables z_i(iε

{1,2,3}), configured and arranged to provide state variables x_i(iε

{1,2,3});

references for variables x_i(iε

{1,2,3});

a control processor including;

a regulation controller receiving variables x_i(iε

{1,2,3}), their references, and a source voltage vector value in stationary coordinates, the regulation controller configured and arranged to provide a source current reference vector in stationary coordinates;

a tracking controller coupled to the regulation controller receiving the source voltage vector value, the source current reference vector, and the source current reference vector value in stationary coordinates, the tracking controller configured and arranged to provide control variables e₁, e₂and e₃;

a balance controller receiving variables x₁, x₂and x₃, and the source voltages values in three-phase coordinates, the balance controller configured and arranged to provided control variables δ

₁, δ

₂and δ

₃;

a duty ratios processor 1 receiving a control variable ε

₁and the control variable δ

₁, and the output voltages across the first pair of output capacitors, the duty ratios processor 1 configured and arranged to provided control signals u_1j(jε

{1,2});

a duty ratios processor 2 receiving a control variable ε

₂and the control variable δ

₂, and the output voltages across the second pair of output capacitors, the duty ratios processor 2 configured and arranged to provided control signals u_2j(jε

{1,2});

a duty ratios processor 3 receiving a control variable ε

₃and the control variable δ

₃, and the output voltages across the third pair of output capacitors, the duty ratios processor 3 configured and arranged to provided control signals u_3j(jε

{1,2}).

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Abstract

The present invention comprises a controller for the cascade H-bridge three-phase multilevel converter used as a shunt active filter. Based on the proposed mathematical model, the controller is designed to compensate harmonic distortion and reactive power due to a nonlinear distorting load. Simultaneously, the controller guarantees regulation and balance of all capacitor voltages. The idea behind the controller is to allow distortion of the current reference during the transients to guarantee regulation and balance of the capacitors voltages. The controller provides the duty ratios for each H-bridge of the cascade multilevel converter.

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22 Claims

1. A controller providing a control vector to a cascade H-bridge three-phase multilevel converter used as a shunt active filter, each phase of the multilevel converter composed of a series connection of two H-bridge cells, each of said phases of the multilevel converter providing a five-level voltage signal, each of said H-bridge cells composed of an H-bridge inverter having an output capacitor and an output resistor coupled across the said H-bridge, each of said H-bridge cells providing an output voltage, each of said phases of the multilevel converter coupled to a corresponding phase of a three-phase power distribution system via a corresponding inductor, each of said phases of the multilevel converter providing an injected current across the corresponding inductor, the said three phases of the multilevel converter connected among them in a star connection, the three phase power distribution system providing a source voltage and a source current for each phase to a corresponding three phase load, the controller comprising:
- a source current module operative to provide a signal indicative of the value of the source current in each phase;
  
  a source voltage module operative to provide a signal indicative of the value of the source voltage in each phase;
  
  an output voltage module operative to provide a signal indicative of the output voltage across the output capacitor of each H-bridge cell;
  
  a three-phase to stationary coordinate converter operative to convert the measured three-phase source current value into a source current value and to convert the three-phase source voltage value into a source voltage value in stationary coordinates;
  
  a voltages transformation processor 1 coupled to the output voltage module and receiving the output voltages across a first pair of output capacitors, the transformation processor 1 configured and arranged to provide variables z₁and y₁;
  
  a voltages transformation processor 2 coupled to the output voltage module and receiving the output voltages across a second pair of output capacitors, the transformation processor 1 configured and arranged to provide variables z₂and y₂;
  
  a voltages transformation processor 3 coupled to the output voltage module and receiving the output voltages across a third pair of output capacitors, the transformation processor 1 configured and arranged to provide variables z₃and y₃;
  
  a coordinates transformation processor coupled to voltages transformation processors 1, 2 and 3, and receiving variables z_i(iε
  
  {1,2,3}), configured and arranged to provide state variables x_i(iε
  
  {1,2,3});
  
  references for variables x_i(iε
  
  {1,2,3});
  
  a control processor including;
  
  a regulation controller receiving variables x_i(iε
  
  {1,2,3}), their references, and a source voltage vector value in stationary coordinates, the regulation controller configured and arranged to provide a source current reference vector in stationary coordinates;
  
  a tracking controller coupled to the regulation controller receiving the source voltage vector value, the source current reference vector, and the source current reference vector value in stationary coordinates, the tracking controller configured and arranged to provide control variables e₁, e₂and e₃;
  
  a balance controller receiving variables x₁, x₂and x₃, and the source voltages values in three-phase coordinates, the balance controller configured and arranged to provided control variables δ
  
  ₁, δ
  
  ₂and δ
  
  ₃;
  
  a duty ratios processor 1 receiving a control variable ε
  
  ₁and the control variable δ
  
  ₁, and the output voltages across the first pair of output capacitors, the duty ratios processor 1 configured and arranged to provided control signals u_1j(jε
  
  {1,2});
  
  a duty ratios processor 2 receiving a control variable ε
  
  ₂and the control variable δ
  
  ₂, and the output voltages across the second pair of output capacitors, the duty ratios processor 2 configured and arranged to provided control signals u_2j(jε
  
  {1,2});
  
  a duty ratios processor 3 receiving a control variable ε
  
  ₃and the control variable δ
  
  ₃, and the output voltages across the third pair of output capacitors, the duty ratios processor 3 configured and arranged to provided control signals u_3j(jε
  
  {1,2}).
- View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22)
- - 2. The controller of claim 1 wherein the source current module is a set of three current sensors.
  - 3. The controller of claim 1 wherein the source voltage module is a set of three voltage sensors.
  - 4. The controller of claim 1 wherein the output voltage module is a set of six voltage sensors.
  - 5. The controller of claim 1 wherein the three-phase to stationary coordinate converter implements the Clarke'"'"'s transformation $T = \sqrt{\frac{2}{3}}$
    - ( 1 - 1 / 2 - 1 / 2 0 3 / 2 - 3 / 2 1 / 2 1 / 2 1 / 2 ) .
  - 6. The controller of claim 1 wherein the voltages transformation processor 1 includes:
    - a first capacitor voltage value ν
      
      _c11multiplied by itself forming a first product value ν
      
      _c11²;
      
      this product multiplied by a first constant value of ½
      
      forming a second product value;
      
      this second product value entering as the first input of the multiplexer module;
      
      a second capacitor voltage ν
      
      _c12multiplied by itself forming a third product value ν
      
      _c12²;
      
      this product multiplied by a second constant value of ½
      
      forming a fourth product value;
      
      this fourth product value entering as the second input of the multiplexer module;
      
      the multiplexer module providing a vector to be operated by a matrix module $[\begin{matrix} 1 & 1 \\ 1 & - 1 \end{matrix}]$ forming a second vector $[\begin{matrix} z_{1} \\ y_{1} \end{matrix}];$ this second vector is introduced to the demultiplexer module providing two variables;
      
      the first variable z₁is the sum of the square of the capacitor voltages multiplied by ½
      
      ;
      
      the second variable y₁is the difference of the square of the capacitor voltages multiplied by ½
      
      ;
      
      these variables expressed by $z_{1} = \frac{v_{C 11}^{2}}{2} + \frac{v_{C 21}^{2}}{2} and y_{1} = \frac{v_{C 11}^{2}}{2} - \frac{v_{C 21}^{2}}{2},$ respectively.
  - 7. The controller of claim 1 wherein the voltages transformation processor 2 has a similar operation as the voltages transformation processor 1, providing the variables $z_{2} = v_{C}$
    - ⁢
      
      21 2 2 + v C ⁢
      
      ⁢
      
      22 2 2 ⁢
      
      ⁢
      
      and ⁢
      
      ⁢
      
      y 2 = v C ⁢
      
      ⁢
      
      21 2 2 - v C ⁢
      
      ⁢
      
      22 2 2 .
  - 8. The controller of claim 1 wherein the voltages transformation processor 3 operates equal to the voltages transformation processor 1, providing the variables $z_{3} = v_{C}$
    - ⁢
      
      31 2 2 + v C ⁢
      
      ⁢
      
      32 2 2 ⁢
      
      ⁢
      
      and ⁢
      
      ⁢
      
      y 3 = v C ⁢
      
      ⁢
      
      31 2 2 - v C ⁢
      
      ⁢
      
      32 2 2 .
  - 9. The controller of claim 1 wherein the coordinates transformation processor includes:
    - a multiplexer module providing a first vector [z₁, z₂, z₃]^T;
      
      this vector to be operated by the matrix module $[\begin{matrix} 1 & 1 & 1 \\ 0 & - \sqrt{3} & \sqrt{3} \\ 2 & - 1 & - 1 \end{matrix}]$ forming a second vector $[\begin{matrix} x_{1} \\ x_{2} \\ x_{3} \end{matrix}] = [\begin{matrix} 1 & 1 & 1 \\ 0 & - \sqrt{3} & \sqrt{3} \\ 2 & - 1 & - 1 \end{matrix}] [\begin{matrix} z_{1} \\ z_{2} \\ z_{3} \end{matrix}];$ this second vector is split in the state variables x₁=z₁+z₂+z₃, x₂=−
      
      √
      
      {square root over (3)}z₂+√
      
      {square root over (3)}z₃and x₃=2z₁−
      
      z₂−
      
      z₃by means of the demultiplexer module.
  - 10. The controller of claim 1, further including a variable V_d, wherein the references for variables x₁, x₂and x₃includes:
    - x*₁=3V_d²as the reference for x₁, x*₂=0 as the reference for x₂, and x*₃=0as the reference for x₃.
  - 11. The controller of claim 1 wherein the regulation controller, included in the control processor, includes:
    - a first difference module forming a first difference value equal to the difference between the state variable x₁and its reference value;
      
      a second difference module forming a second difference value equal to the difference between the state variable x₂and zero;
      
      a third difference module forming a third difference value equal to the difference between the state variable x₃and zero;
      
      a first proportional-integral scheme, with proportional constant k_p1and integral constant k_i1, operating over the first difference value forming $G_{1} = g_{1} v_{S, RMS}^{2} = - k_{p 1} {\tilde{x}}_{1} - k_{i 1} \int_{0}^{t} {\tilde{x}}_{1} ⅆ t,$ that is, the apparent conductance observed by the source;
      
      a second proportional-integral scheme, with proportional constant k_p2and integral constant k_i2, operating over the second difference value forming $G_{2} = g_{2} v_{S, RMS}^{2} = - k_{p 2} x_{2} - k_{i 2} \int_{0}^{t} x_{2} ⅆ t;$ a third proportional-integral scheme, with proportional constant and integral constant k_p3and integral constant k_i3, operating over the third difference value forming $G_{3} = g_{3} v_{S, RMS}^{2} = - k_{p 3} x_{3} - k_{i 3} \int_{0}^{t} x_{3} ⅆ t;$ a scale factor multiplying the source voltage vector in stationary coordinates forming a scaled source voltage vector $\frac{v_{S αβ}}{v_{S, RMS}^{2}};$ the G₁=g₁ν
      
      _S,RMS²is multiplied by the scaled source voltage vector $\frac{v_{S αβ}}{v_{S, RMS}^{2}}$ forming a first component of the current reference $g_{1} [\begin{matrix} 1 & 0 \\ 0 & 1 \end{matrix}] v_{S αβ} = g_{1} M_{1} v_{S αβ};$ the G₂=g₂ν
      
      _S,RMS²is multiplied by the scaled source voltage vector $\frac{v_{S αβ}}{v_{S, RMS}^{2}}$ forming a second component of the current reference $g_{2} [\begin{matrix} 1 & 0 \\ 0 & - 1 \end{matrix}] v_{S αβ} = g_{2} M_{2} v_{S αβ};$ the G₃=g₃ν
      
      _S,RMS²is multiplied by the scaled source voltage vector $\frac{v_{S αβ}}{v_{S, RMS}^{2}}$ forming a third component of the current reference $g_{3} [\begin{matrix} 0 & 1 \\ 1 & 0 \end{matrix}] v_{S α β} = g_{3} M_{3} v_{S α β};$ a first adder module adding the first, second and third component of the current reference to form an overall current reference vector given by $\begin{matrix} i_{S αβ}^{*} = g_{1} [\begin{matrix} 1 & 0 \\ 0 & 1 \end{matrix}] v_{S αβ} + g_{2} [\begin{matrix} 1 & 0 \\ 0 & - 1 \end{matrix}] v_{S αβ} + g_{3} [\begin{matrix} 0 & 1 \\ 1 & 0 \end{matrix}] v_{S αβ} \\ = g_{1} M_{1} v_{S αβ} + g_{2} M_{2} v_{S αβ} + g_{3} M_{3} v_{S αβ} . \end{matrix}$
  - 12. The controller of claim 1 wherein the tracking controller, included in the control processor, includes:
    - a first difference module forming a current error signal equal to the difference between the source current vector and a reference current vector ĩ
      
      _Sα
      
      β=(i_Sα
      
      β−
      
      i*_Sα
      
      β) in stationary coordinates;
      
      a first gain factor K₁multiplying a current error vector providing a proportional control signal K₁ĩ
      
      _Sα
      
      β;
      
      a harmonic compensator including a plurality of second order harmonic filters of the form $\frac{2 γ_{k} s}{s^{2} + k^{2} ω_{0}^{2}},$ each having a resonant frequency tuned at selected harmonic components to compensate kω
      
      ₀, kε
      
      {1,3,5, . . . }, where γ
      
      _kis the positive gain of the k-th harmonic filter, each of the plurality of second order harmonic filters receiving the current error vector and providing a plurality of filtered outputs;
      
      the harmonic compensator providing a harmonic control signal formed by the addition of the plurality of filtered outputs, that is, $\sum_{k \in {1, 3, 5, \dots}} diag {\frac{2 γ_{k} s}{s^{2} + k^{2} ω^{2}}, \frac{2 γ_{k} s}{s^{2} + k^{2} ω^{2}}} {\tilde{i}}_{S αβ};$ a first adder module adding the proportional control signal, the harmonic control signal and the source voltage vector in stationary coordinates forming a control vector $ɛ_{αβ} = K_{1} {\tilde{i}}_{S αβ} + v_{S αβ} + \sum_{k \in {1, 3, 5, \dots}} diag {\frac{2 γ_{k} s}{s^{2} + k^{2} ω^{2}}, \frac{2 γ_{k} s}{s^{2} + k^{2} ω^{2}}} {\tilde{i}}_{S αβ};$ a stationary to three-phase coordinates converter module receiving the control vector and providing the control vector ε
      
      ₁₂₃with ε
      
      _α
      
      β;
      
      the control vector in three-phase coordinates is split in control signals ε
      
      ₁, ε
      
      ₂and ε
      
      ₃by means of the demultiplexer.
  - 13. The controller of claim 1 wherein the balance controller, included in the control processor, includes:
    - a first proportional-integral scheme, with proportional constant β
      
      _p1and integral constant ε
      
      _i1, operating over a state variable y₁providing an auxiliary variable $ρ_{1} = - β_{p 1} y_{1} - β_{i 1} \int_{0}^{t} y_{1} ⅆ t;$ a second proportional-integral scheme, with proportional constant β
      
      _p2and integral constant β
      
      _i2,operating over a state variable y₂providing an auxiliary variable $ρ_{2} = - β_{p 2} y_{2} - β_{i 2} \int_{0}^{t} y_{2} ⅆ t;$ a third proportional-integral scheme, with proportional constant β
      
      _p3and integral constant β
      
      _i3, operating over a state variable y₃providing an auxiliary variable $ρ_{3} = - β_{p 3} y_{3} - β_{i 3} \int_{0}^{t} y_{3} ⅆ t;$ the auxiliary variable ρ
      
      ₁multiplied by a variable ν
      
      _S1forming a control variable δ
      
      ₁=ρ
      
      ₁ν
      
      _S1;
      
      the auxiliary variable ρ
      
      ₂multiplied by ν
      
      _S2forming the control variable δ
      
      ₂=ρ
      
      ₂ν
      
      _S2;
      
      the auxiliary variable ρ
      
      ₃multiplied by ν
      
      _S3forming the control variable δ
      
      ₃=ρ
      
      ₃ν
      
      _S3.
  - 14. The controller of claim 1 wherein the duty ratios processor 1, included in the control processor, includes:
    - a multiplexer module forming a control vector with two control variables ε
      
      ₁and δ
      
      ₁;
      
      a matrix module operating over the control vector providing an auxiliary vector of the combined control variables;
      
      a demultiplexer module providing the sum and the difference of the control variables, that is, (ε
      
      ₁+δ
      
      ₁) and (ε
      
      ₁−
      
      δ
      
      ₁);
      
      a first divisor module dividing the sum of the control variables over the value of a first capacitor voltage forming a first product value;
      
      a second divisor module dividing the difference of the control variables over the value of a second capacitor voltage forming a second product value;
      
      the first product multiplied by a first constant value of ½
      
      forming the first control signal;
      
      the second product multiplied by a second constant value of ½
      
      forming the second control signal;
      
      the first control signal is expressed by $u_{11} = \frac{ɛ_{1} + δ_{1}}{2 v_{C 11}}$ and the second control signal is expressed by $u_{12} = \frac{ɛ_{1} - δ_{1}}{2 v_{C 12}} .$
  - 15. The controller of claim 1 wherein the duty ratios processor 2, included in the control processor, operates equal to the duty ratios processor 1, providing the control signals $u_{21} = ɛ$
    - 2 + δ
      
      2 2 ⁢
      
      v C ⁢
      
      ⁢
      
      21 ⁢
      
      ⁢
      
      and ⁢
      
      ⁢
      
      u 22 = ɛ
      
      2 - δ
      
      2 2 ⁢
      
      v C ⁢
      
      ⁢
      
      22 .
  - 16. The controller of claim 1 wherein the duty ratios processor 3, included in the control processor, operates equal to the duty ratios processor 1, providing the control signals $u_{31} = ɛ$
    - 3 + δ
      
      3 2 ⁢
      
      v C ⁢
      
      ⁢
      
      31 ⁢
      
      ⁢
      
      and ⁢
      
      ⁢
      
      u 32 = ɛ
      
      3 - δ
      
      3 2 ⁢
      
      v C ⁢
      
      ⁢
      
      32 .
  - 17. The regulation controller of claim 11 wherein the proportional-integral scheme constants k_p1, k_i1, k_p2, k_i2, k_p3and k_i3are predetermined design constants that are greater than zero.
  - 18. The balance controller of claim 13 wherein the proportional-integral scheme constants β
    - _p1, β
      
      _i1, β
      
      _p2, β
      
      _i2, β
      
      _p3and β
      
      _i3are predetermined design constants that are greater than zero.
  - 19. The tracking controller of claim 12 wherein the gain K₁is a predetermined design constant that is greater than zero.
  - 20. The controller of claim 11 wherein the source current reference vector $\begin{matrix} i_{S} \end{matrix}$
    - ⁢
      
      α
      
      β
      
      * = g 1 ⁡
      
      [ 1 0 0 1 ] ⁢
      
      v S ⁢
      
      ⁢
      
      α
      
      β
      
      + g 2 ⁡
      
      [ 1 0 0 - 1 ] ⁢
      
      v S ⁢
      
      ⁢
      
      α
      
      β
      
      + g 3 ⁡
      
      [ 0 1 1 0 ] ⁢
      
      v S ⁢
      
      ⁢
      
      α
      
      β
      
      = g 1 ⁢
      
      M 1 ⁢
      
      v S ⁢
      
      ⁢
      
      α
      
      β
      
      + g 2 ⁢
      
      M 2 ⁢
      
      v S ⁢
      
      ⁢
      
      α
      
      β
      
      + g 3 ⁢
      
      M 3 ⁢
      
      v S ⁢
      
      ⁢
      
      α
      
      β
      
      includes two extra terms g₂M₂ν
      
      _Sα
      
      β and g₃M₃ν
      
      _Sα
      
      β associated to control inputs g₂and g₃, respectively, that distort this reference current in order to balance the capacitor voltages.
  - 21. The current reference of claim 20 wherein the two extra control inputs g₂and g₃vanish once the capacitor voltages are balanced, thus, making the current reference i*_Sα
    - β
      
      proportional to the source voltage ν
      
      _Sα
      
      β in the steady state.
  - 22. The controller of claim 1 wherein the number of levels of the multilevel converter can be scaled to a higher number with corresponding modifications and increase of control and sensed signals.

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Litigation Campaign Assessment

Current Assignee
Instituto Potosino de Investigacion Cientifica y Tecnologica
Original Assignee
Instituto Potosino de Investigacion Cientifica y Tecnologica
Inventors
Valdez Fernandez, Andres Alejandro, Martinez Montejano, Misael Fransisco, Torres Olguin, Raymundo Enrique, Escobar Valderrama, Gerardo
Primary Examiner(s)
Sterrett; Jeffrey L
Assistant Examiner(s)
Finch, III; Fred E

Application Number

US11/975,231
Publication Number

US 20090102436A1
Time in Patent Office

929 Days
Field of Search

323/207, 363/40, 363/43, 363/56.02, 363/65, 363/71, 363/98, 363/132
US Class Current

323/207
CPC Class Codes

H02J 3/1857   wherein such bridge convert...

H02M 1/0003   Details of control, feedbac...

H02M 7/4835   comprising two or more cell...

Y02E 40/20   Active power filtering [APF]

Controller for the three-phase cascade multilevel converter used as shunt active filter in unbalanced operation with guaranteed capacitors voltages balance

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Controller for the three-phase cascade multilevel converter used as shunt active filter in unbalanced operation with guaranteed capacitors voltages balance

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