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Controller for the three-phase cascade multilevel converter used as shunt active filter in unbalanced operation with guaranteed capacitors voltages balance

  • US 7,710,082 B2
  • Filed: 10/18/2007
  • Issued: 05/04/2010
  • Est. Priority Date: 10/18/2007
  • Status: Expired due to Fees
First Claim
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1. A controller providing a control vector to a cascade H-bridge three-phase multilevel converter used as a shunt active filter, each phase of the multilevel converter composed of a series connection of two H-bridge cells, each of said phases of the multilevel converter providing a five-level voltage signal, each of said H-bridge cells composed of an H-bridge inverter having an output capacitor and an output resistor coupled across the said H-bridge, each of said H-bridge cells providing an output voltage, each of said phases of the multilevel converter coupled to a corresponding phase of a three-phase power distribution system via a corresponding inductor, each of said phases of the multilevel converter providing an injected current across the corresponding inductor, the said three phases of the multilevel converter connected among them in a star connection, the three phase power distribution system providing a source voltage and a source current for each phase to a corresponding three phase load, the controller comprising:

  • a source current module operative to provide a signal indicative of the value of the source current in each phase;

    a source voltage module operative to provide a signal indicative of the value of the source voltage in each phase;

    an output voltage module operative to provide a signal indicative of the output voltage across the output capacitor of each H-bridge cell;

    a three-phase to stationary coordinate converter operative to convert the measured three-phase source current value into a source current value and to convert the three-phase source voltage value into a source voltage value in stationary coordinates;

    a voltages transformation processor 1 coupled to the output voltage module and receiving the output voltages across a first pair of output capacitors, the transformation processor 1 configured and arranged to provide variables z1 and y1;

    a voltages transformation processor 2 coupled to the output voltage module and receiving the output voltages across a second pair of output capacitors, the transformation processor 1 configured and arranged to provide variables z2 and y2;

    a voltages transformation processor 3 coupled to the output voltage module and receiving the output voltages across a third pair of output capacitors, the transformation processor 1 configured and arranged to provide variables z3 and y3;

    a coordinates transformation processor coupled to voltages transformation processors 1, 2 and 3, and receiving variables zi (iε

    {1,2,3}), configured and arranged to provide state variables xi (iε

    {1,2,3});

    references for variables xi (iε

    {1,2,3});

    a control processor including;

    a regulation controller receiving variables xi (iε

    {1,2,3}), their references, and a source voltage vector value in stationary coordinates, the regulation controller configured and arranged to provide a source current reference vector in stationary coordinates;

    a tracking controller coupled to the regulation controller receiving the source voltage vector value, the source current reference vector, and the source current reference vector value in stationary coordinates, the tracking controller configured and arranged to provide control variables e1, e2 and e3;

    a balance controller receiving variables x1, x2 and x3, and the source voltages values in three-phase coordinates, the balance controller configured and arranged to provided control variables δ

    1, δ

    2 and δ

    3;

    a duty ratios processor 1 receiving a control variable ε

    1 and the control variable δ

    1, and the output voltages across the first pair of output capacitors, the duty ratios processor 1 configured and arranged to provided control signals u1j (jε

    {1,2});

    a duty ratios processor 2 receiving a control variable ε

    2 and the control variable δ

    2, and the output voltages across the second pair of output capacitors, the duty ratios processor 2 configured and arranged to provided control signals u2j (jε

    {1,2});

    a duty ratios processor 3 receiving a control variable ε

    3 and the control variable δ

    3, and the output voltages across the third pair of output capacitors, the duty ratios processor 3 configured and arranged to provided control signals u3j (jε

    {1,2}).

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