Stacked inverter delay chain

• US 7,710,160 B2
• Filed: 02/26/2008
• Issued: 05/04/2010
• Est. Priority Date: 06/08/2004
• Status: Active Grant

• Current Assignee: Intellectual Ventures Funding LLC (Intellectual Ventures LLC)
• Original Assignee: Intellectual Ventures Funding LLC (Intellectual Ventures LLC)
• Inventors: Masleid, Robert P., Burr, James B.
• Primary Examiner(s): Chang; Daniel D
• Application Number:
  US12/037,884
• Publication Number:
  US 20080144407A1
• Time in Patent Office: 798 Days
• Field of Search: 326/87, 326/119, 326/121, 326/122, 327/281, 327/288
• US Class Current: 326/121
• CPC Class Codes: H03K 17/6872 using complementary field-effect transistors
• CPC Class Codes: H03K 19/00361 in field effect transistor circuits
• CPC Class Codes: H03K 5/1252 Suppression or limitation of noise or interference specially adapted for transmission systems H04B15/00, H04L25/08
• CPC Class Codes: H03K 5/133 using a chain of active delay devices

Abstract

Stacked inverter delay chains. In accordance with a first embodiment of the present invention, a series stack of two p-type devices is coupled to a series stack of three n-type devices, forming a stacked inverter comprising desirable delay, die area and power characteristics. Two stacked inverters are coupled together to form a stacked inverter delay chain that is more efficient in terms of die area, active and passive power consumption than conventional delay chains comprising conventional inverters.

Claims

1. A circuit comprising:

a first stacked inverter including a first plurality of active devices of a first type and a second plurality of active devices of a second type; and

a second stacked inverter including a third plurality of active device of the first type and a fourth plurality of active devices of the second type, wherein the output of the first stacked inverter is coupled to the input of the second staked inverter, and wherein a total number of the third plurality is not equal to the fourth plurality in the second stacked inverter.

2. The circuit of claim 1, wherein the active device is a field effect transistor.

3. The circuit of claim 1, wherein the active device is a metal oxide semiconductor filed effect transistor.

4. The circuit of claim 1, wherein the first stacked inverter and second stacked inverter are substantially the same.

5. The circuit of claim 1, wherein the first type of active device is a p-type device and the second type of active device is an n-type device.

6. A stacked inverter comprising:

a first plurality of transistors of a first type coupled in series with each other, wherein a first end of the first plurality of transistors is coupled to a first potential; and

a second plurality of transistors of a second type coupled in series with each other, wherein a first end of the second plurality of transistors is coupled to a second potential, the gates of the first and second plurality of transistors are coupled together as an input, the second end of the first and second plurality of transistors are coupled together as an output and a total number of transistors of the first type is different than a total number of the second type.

7. The stacked inverter of claim 6, wherein the transistor is a field effect transistor.

8. The stacked inverter of claim 6, wherein the transistor is a metal oxide semiconductor filed effect transistor.

9. The stacked inverter of claim 6, wherein the first type of transistor is a type transistor and the second type of transistor is an n-type transistor.

10. The stacked inverter of claim 6, wherein:

the first plurality of transistors of the first type comprises three n-type transistors; and

the second plurality of transistors of the second type comprises two p-type transistors.

11. A method of fabricating a stacked inverter comprising:

forming a first plurality of transistors from sequential p-type diffusions in an n-well;

forming a second plurality of transistors from sequential n-type diffusions in a p-well, wherein a total number of the first plurality is different from a total number of the second plurality;

forming a first metallization coupling a first end of the sequential p-type diffusions and a first end of the sequential n-type diffusions as an output of the stacked inverter;

forming a second metallization coupling a second end of the sequential p-type diffusions to a first potential;

forming a third metallization coupled a second end of the sequential n-type diffusions to a second potential; and

forming a fourth metallization coupling a gate of each of the first and second plurality of transistors as an input of the staked inverter.

12. The method according to claims 11, wherein the transistor is a field effect transistor.

13. The method according to claim 11, wherein the transistor is a metal oxide semiconductor filed effect transistor.

14. The method according to claim 11, wherein:

the first plurality of transistors of the first type comprises three n-type transistors; and

the second plurality of transistors of the second type comprises two p-type transistors.