Semi-volatile NAND flash memory

• US 7,710,777 B1
• Filed: 12/14/2007
• Issued: 05/04/2010
• Est. Priority Date: 12/20/2006
• Status: Active Grant

• Current Assignee: Marvell Asia Pte Limited (Marvell Technology Group Limited)
• Original Assignee: Marvell International Limited (Marvell Technology Group Limited)
• Inventors: Montierth, Mark D., Keithley, Douglas G., Briggs, Randall D.
• Primary Examiner(s): MAI, SON LUU
• Application Number:
  US11/957,269
• Time in Patent Office: 872 Days
• Field of Search: 365/185.11, 365/185.09
• US Class Current: 365/185.09
• CPC Class Codes: G11C 16/06 Auxiliary circuits, e.g. for writing into memory
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/3431 Circuits or methods to detect disturbed nonvolatile memory cells, e.g. which still read as programmed but with threshold less than the program verify threshold or read as erased but with threshold greater than the erase verify threshold, and to reverse the disturbance via a refreshing programming or erasing step
• CPC Class Codes: G11C 16/349 Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles

Abstract

Semi-volatile NAND flash memory systems, apparatuses, and methods for use are described herein. According to various embodiments, a semi-volatile NAND flash memory may be partitioned into various retention regions. Other embodiments may be described and claimed.

Claims

1. A semi-volatile NAND flash system, comprising:

a NAND flash memory cell array partitioned into a plurality of retention regions including a first retention region and a second retention region; and

a memory controller configured to selectively store data into one of the plurality of retention regions based on an expected storage duration associated with the data;

wherein the first retention region is configured to store data having an expected storage duration that is equal to or less than a first threshold; and

wherein the second retention region is configured to store data having an expected storage duration that is equal to or less than a second threshold, the first threshold being greater than the second threshold.

2. The semi-volatile NAND flash system of claim 1, wherein the memory controller is further configured to store retained data in the first retention region.

3. The semi-volatile NAND flash system of claim 1, wherein the plurality of retention regions include a third retention region;

wherein the third retention region is configured to store data having an expected storage duration that is equal to or less than a third threshold, the second threshold being greater than the third threshold.

4. The semi-volatile NAND flash system of claim 3, wherein the memory controller is further configured to refresh at least one of the data in the second retention region and the data in the third retention region after a predetermined amount of write cycles.

5. The semi-volatile NAND flash system of claim 4, wherein the memory controller is further configured to repeat the refresh after a predetermined amount of time.

6. The semi-volatile NAND flash system of claim 3, wherein the first, second, and third retention regions have different sizes.

7. The semi-volatile NAND flash system of claim 3, wherein the memory controller is further configured to perform wear-leveling on at least one of the first retention region, the second retention region, and the third retention region.

8. The semi-volatile NAND flash system of claim 1, wherein the memory controller is further configured to store transient data in the second retention region.

9. A method comprising:

partitioning a NAND flash memory cell into a plurality of retention regions, including a first retention region and a second retention region;

selectively storing data into one of the plurality of retention regions based on an expected storage duration associated with the data, wherein said selectively storing data further comprises;

storing data, having an expected storage duration that is equal to or less than a first threshold, in the first retention region; and

storing data, having an expected storage duration that is equal to or less than a second threshold, in the second retention region, wherein the first threshold is greater than the second threshold.

10. The method of claim 9, further comprising:

storing retained data in the first retention region.

11. The method of claim 9, further comprising:

storing transient data in the second retention region.

12. The method of claim 9, wherein the plurality of retention regions include a third retention region, wherein said selectively storing data into one of the plurality of retention regions further comprises:

storing data, having an expected storage duration that is equal to or less than a third threshold, in the third retention region, wherein the second threshold is greater than the third threshold.

13. The method of claim 12, further comprising:

refreshing at least one of the data in the second retention region and the data in the third retention region after a predetermined amount of write cycles.

14. The method of claim 13, further comprising:

repeating the refresh after a predetermined amount of time.

15. The method of claim 13, further comprising:

performing wear-leveling on at least one of the first retention region, the second retention region, and the third retention region.