Cascading of gigabit switches

• US 7,710,954 B2
• Filed: 06/07/2006
• Issued: 05/04/2010
• Est. Priority Date: 06/09/2000
• Status: Expired due to Fees

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Kalkunte, Mohan, Ambe, Shekhar
• Primary Examiner(s): Phunkulh; Bob A
• Application Number:
  US11/447,915
• Publication Number:
  US 20060251085A1
• Time in Patent Office: 1,427 Days
• Field of Search: None
• US Class Current: 370/386
• CPC Class Codes: H04L 12/462 LAN interconnection over a bridge based backbone
• CPC Class Codes: H04L 45/00 Routing or path finding of packets in data switching networks routing or path finding in wireless networks H04W40/00
• CPC Class Codes: H04L 45/16 Multipoint routing
• CPC Class Codes: H04L 45/245 Link aggregation, e.g. trunking
• CPC Class Codes: H04L 45/52 Multiprotocol routers
• CPC Class Codes: H04L 45/742 Route cache; Operation thereof
• CPC Class Codes: H04L 47/10 Flow control; Congestion control
• CPC Class Codes: H04L 47/2458 Modification of priorities while in transit
• CPC Class Codes: H04L 47/266 Stopping or restarting the source, e.g. X-on or X-off
• CPC Class Codes: H04L 47/29 using a combination of thresholds
• CPC Class Codes: H04L 47/32 by discarding or delaying data units, e.g. packets or frames
• CPC Class Codes: H04L 49/102 using shared medium, e.g. bus or ring
• CPC Class Codes: H04L 49/109 Integrated on microchip, e.g. switch-on-chip
• CPC Class Codes: H04L 49/15 Interconnection of switching modules
• CPC Class Codes: H04L 49/3009 Header conversion, routing tables or routing tags
• CPC Class Codes: H04L 49/3018 Input queuing
• CPC Class Codes: H04L 49/3036 Shared queuing
• CPC Class Codes: H04L 49/351 for local area network [LAN], e.g. Ethernet switches
• CPC Class Codes: H04L 49/352 Gigabit ethernet switching [GBPS]
• CPC Class Codes: H04L 49/354 for supporting virtual local area networks [VLAN]
• CPC Class Codes: H04L 49/506 : Backpressure
• CPC Class Codes: H04L 49/508 : Head of Line Blocking Avoidance
• CPC Class Codes: H04L 49/602 : Multilayer or multiprotocol switching, e.g. IP switching
• CPC Class Codes: H04L 69/22 : Parsing or analysis of headers
• CPC Class Codes: Y02D 30/50 : in wire-line communication networks, e.g. low power modes or reduced link rate

Abstract

A method of handling data packets in a series of network switches includes receiving an incoming data packet at a data port of a first switch of the series of network switches. A module id bitmap of the incoming data packet is resolved and a bit corresponding to the first switch of the module id bitmap is examined to determine if the bit is set. A destination address of the incoming data packet is resolved when the corresponding bit is set and the incoming data packet is forwarded or dropped based on the destination address. When the corresponding bit is not set, the incoming data packet is forwarded to a next switch of the series of network switches. A network switch configured to allow for cascading of data packets is also disclosed.

Claims

1. A method of handling data packets in a series of network switches, the method comprising:

receiving an incoming data packet at a data port of a first switch of the series of network switches, the incoming data packet including a resolved module ID bitmap;

determining if a bit of the resolved module ID bitmap corresponding to the first switch is set;

determining a destination address of the incoming data packet when the corresponding bit is set;

forwarding or dropping the incoming data packet based on the destination address when the corresponding bit is set; and

conducting normal address resolution logic (ARL) if the corresponding bit is determined to be set and flipping the corresponding bit in the module ID bitmap.

2. The method of claim 1, further comprising forwarding the incoming data packet to a next switch of the series of network switches when the corresponding bit is not set.

3. The method of claim 2, further comprising:

flipping the corresponding bit after forwarding the incoming data packet to the destination address; and

forwarding, after flipping the corresponding bit, the incoming data packet to a next switch of the series of network switches when the module ID bitmap is nonzero.

4. The method of claim 1, further comprising determining a mirroring field of the incoming data packet and forwarding the incoming data packet to a mirroring port based on the determined mirroring field.

5. The method of claim 1, wherein forwarding the packet comprises forwarding the data packet through a 10 Gigabit Ethernet interface.

6. The method of claim 1, wherein resolving the module ID bitmap of the incoming data packet is performed by an interconnect port interface controller (IPIC).

7. The method of claim 6, wherein the IPIC appends a module header to the forwarded data packet, the appended module header including the module ID bitmap obtained from a P-channel field.

8. The method of claim 1, further comprising determining if the module ID bitmap is not zero, and if the module ID bitmap is determined to be not zero, then an interconnect port interface controller (IPIC) port is included in a port bitmap and sent to a memory management unit, and if the module ID bitmap is zero, then the port bitmap does not include the IPIC port.

9. The method of claim 1, further comprising determining if an egress port associated with the destination address is in a forwarding state before forwarding the incoming data packet.

10. A network switch in a series of network switches comprising:

means for receiving an incoming data packet through a data port of a first switch of the series of network switches;

means for resolving a module ID bitmap of the incoming data packet and determining if a bit corresponding to the first switch of the module ID bitmap is set;

means for resolving a destination address of the incoming data packet when the corresponding bit is set and forwarding or dropping the incoming data packet based on the destination address;

means for forwarding the incoming data packet to a next switch of the series of network switches when the corresponding bit is not set; and

means for conducting normal address resolution logic (ARL) if the corresponding bit is determined to be set and flipping the corresponding bit in the module ID bitmap.

11. The network switch of claim 10, further comprising means for flipping the corresponding bit after forwarding the incoming data packet and means for forwarding the incoming data packet to a next switch of the series of network switches when the module ID bitmap is nonzero.

12. The network switch of claim 11, further comprising:

means for resolving a mirroring field of the incoming data packet; and

means for forwarding the incoming data packet to a mirroring port based on the mirroring field.

13. The network switch of claim 10, wherein the means for forwarding the incoming data packet to a next switch of the series of network switches comprises means for forwarding the incoming data packet through a 10 Gigabit Ethernet interface.

14. The network switch of claim 10, wherein resolving the module ID bitmap of the incoming data packet is performed by an interconnect port interface controller (IPIC).

15. The network switch of claim 14, wherein the IPIC operates to append a module header to the forwarded data packet, the appended module header including the module ID bitmap obtained from a P-channel field.

16. The network switch of claim 10, wherein the network switch is configured to determine if the module ID bitmap is not zero, and if the module ID bitmap is determined to be not zero, then an interconnect port interface controller (IPIC) port is included in a port bitmap and sent to a memory management unit, and if the module ID bitmap is zero, then the port bitmap does not include the IPIC port.

17. A series of network switches, wherein one switch in the series of network switches comprises:

first and second transmitting and receiving data port interfaces; and

a memory management unit communicating data from the first data port interface and the second data port interface and a memory on a communication channel,

wherein the second data port interface is interconnected with other network switches of the series via a simplex connection and is configured to;

resolve a module ID bitmap from a header of an incoming data packet;

forward the incoming data packet over the simplex interconnection based on the resolved module ID; and

conduct normal address resolution logic (ARL) if the corresponding bit is determined to be set and flip the corresponding bit in the module ID bitmap.

18. The series of network switches recited in claim 17, wherein the simplex interconnection comprises a stack link.

19. The series of network switches recited in claim 17, wherein the second data port interface is further configured to determine if a bit corresponding to a first switch of the resolved module ID bitmap is set, to determine a destination address of the incoming data packet when the corresponding bit is set, and to forward the incoming data packet based on the destination address if the corresponding bit is set.

20. The series of network switches recited in claim 19, wherein the second data port interface is further configured to forward the incoming data packet to a next switch of the series of network switches when the corresponding bit is not set.

21. The series of network switches recited in claim 20, wherein the second data port interface is further configured to flip the corresponding bit after forwarding the incoming data packet and forward the incoming data packet to a next switch of the series of network switches when the module ID bitmap is nonzero.