Bandwidth control and power saving by interface aggregation

• US 7,711,873 B1
• Filed: 01/10/2008
• Issued: 05/04/2010
• Est. Priority Date: 01/10/2007
• Status: Active Grant

• Current Assignee: Marvell Asia Pte Limited (Marvell Technology Group Limited)
• Original Assignee: Marvell International Limited (Marvell Technology Group Limited)
• Inventors: Zaarur, Ofer
• Primary Examiner(s): Dang; Khanh
• Application Number:
  US12/008,339
• Time in Patent Office: 845 Days
• Field of Search: 710 10- 12, 710/14, 710 16- 18, 710/35, 710/56, 710/59, 710/60
• US Class Current: 710/35
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/3253 Power saving in bus
• CPC Class Codes: G06F 13/124 where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management
• CPC Class Codes: Y02D 30/50 in wire-line communication networks, e.g. low power modes or reduced link rate

Abstract

A first processor that executes at least one application or process includes a first interface module that interfaces the first processor to a second processor and that includes N interfaces. N is an integer greater than 1. The first processor also includes a first communication control module (CCM) that selects M of the N interfaces based on bandwidth requested by the at least one application to transmit data generated by the at least one application to the second processor.

Claims

1. A first processor that executes an application, the first processor comprising:

a first interface module that interfaces said first processor to a second processor, said first interface module including N interfaces, where N is an integer greater than 1; and

a first communication control module (CCM) that is coupled to said first interface module and that selects M interfaces from said N interfaces based on bandwidth requested by said application to transmit data generated by said application to said second processor, where M is an integer and 1≦

M≦

N,

wherein said first CCM comprises;

a first transmit buffer that buffers first data generated by said application; and

a first splitter module that receives said first data from said transmit buffer and outputs said first data to said M interfaces,

wherein when M>

1, said first splitter module splits said first data into first portions and outputs said first portions to said M interfaces based on data rates of said M interfaces.

2. The first processor of claim 1, wherein said first CCM sets interfaces other than said M interfaces to one of low-power and power-off modes.

3. A system comprising said first processor and said second processor of claim 1, wherein said second processor comprises:

a second interface module that communicates with said first interface module and that includes P interfaces, where P is an integer greater than 1; and

a second CCM that selects R interfaces from said P interfaces to transmit data to said first processor, where R is an integer and 1≦

R≦

P.

4. The system of claim 3, wherein said second CCM sets interfaces of said second interface module other than said R interfaces to one of low-power and power-off modes.

5. The system of claim 3, wherein said second CCM selects said R interfaces to transmit data to said first processor based on a rate at which said second processor receives data from devices other than said first processor.

6. The system of claim 3, wherein P=N.

7. The system of claim 3, wherein said first processor and said second processor are implemented by one of an integrated circuit (IC) and two separate devices.

8. The system of claim 3, wherein said N and P interfaces include at least one of universal asynchronous receiver/transmitters (UARTs), universal synchronous bus (USB) interfaces, secure digital input/output (SDIO) interfaces, and serial peripheral interfaces (SPIs).

9. The system of claim 3, wherein said first CCM further comprises:

a first aggregator module that reorders second portions of data received from said M interfaces in an order transmitted by said R interfaces; and

a first receive buffer that stores said second portions and that outputs said second portions to said application.

10. The system of claim 9, wherein said first splitter splits said data into a plurality of portions based on a number said M interfaces and said R interfaces that are active.

11. The system of claim 9, wherein said first CCM selects said M interfaces based on amounts of data in at least one of said first transmit buffer and said first receive buffer.

12. The system of claim 9, wherein said first transmit buffer and said first receive buffer are circular buffers.

13. The system of claim 3, wherein said second CCM comprises:

a second transmit buffer that buffers second data received from devices other than said first processor; and

a second splitter module that receives said second data from said second transmit buffer and outputs said second data to said R interfaces,

wherein when R>

1, said second splitter module splits said second data into second portions and that outputs said second portions to said R interfaces based on data rates of said R interfaces.

14. The system of claim 13, wherein said second CCM further comprises:

a second aggregator module that reorders third portions of data received from said R interfaces in an order transmitted by said M interfaces; and

a second receive buffer that stores said third portions for communicating said third portions to said devices.

15. The system of claim 14, wherein said second CCM selects said R interfaces based on amounts of data in at least one of said transmit buffer and said receive buffer.

16. The system of claim 14, wherein said second transmit buffer and said second receive buffer are circular buffers.

17. The system of claim 3, wherein said first processor is implemented by a first device, and wherein said second processor is implemented by a second device that is separate from said first device.

18. The system of claim 17, wherein said first CCM adds sequence identifiers to portions of data transmitted by said M interfaces when M>

1, and wherein said second CCM reorders said portions received by said R interfaces based on said sequence identifiers.

19. A device comprising the system of claim 3, wherein said device includes one of a communication device, a mass storage device, a transmitter, and a receiver, wherein said communication device includes one of a mobile computing device, wireless network device, and a cellular phone, and wherein said mass storage device includes a hard disk drive (HDD), a compact disc (CD) drive, and a digital versatile disc (DVD) drive.

20. The first processor of claim 2, wherein said first CCM sets one of said low-power and power-off modes based on a predetermined amount of time that at least one interface of said N interfaces is not at least one of transmitting and receiving said first data.

21. The first processor of claim 1, wherein said first processor comprises an application processor (AP) and said second processor comprises a communication processor (CP).

22. A method for executing an application, the method comprising:

interfacing a first processor to a second processor via N interfaces, where N is an integer greater than 1;

selecting M interfaces from said N interfaces based on bandwidth requested by said application to transmit data generated by said application to said second processor, where M is an integer and 1≦

M≦

N;

buffering data generated by said application;

splitting said data into first portions when M>

1; and

outputting said first portions to said M interfaces based on data rates of said M interfaces when M>

1.

23. The method of claim 22, further comprising setting interfaces other than said M interfaces to one of low-power and power-off modes based on a predetermined amount of time that at least one interface of said N interfaces is not at least one of transmitting and receiving said data.

24. The method of claim 22, further comprising selecting R interfaces from P interfaces to

transmit data to said first processor, wherein a first interface module includes said N interfaces, and a second interface module includes said P interfaces and communicates with said first interface, where R is an integer and 1≦

R≦

P, and where P is an integer greater than 1.

25. The method of claim 24, further comprising selecting said R interfaces to transmit data to said first processor based on a rate at which said second processor receives data from devices other than said first processor.

26. The method of claim 24, wherein P=N.

27. The method of claim 24, further comprising:

reordering second portions of data received from said M interfaces in an order transmitted by said R interfaces;

storing said second portions; and

outputting said second portions to said application.

28. The method of claim 27, further comprising splitting said data into a plurality of portions based on a number said M interfaces and said R interfaces that are active.

29. The method of claim 24, further comprising:

buffering data received from devices other than said first processor;

splitting said data into second portions; and

outputting said second portions to said R interfaces based on data rates of said R interfaces when R>

1.

30. The method of claim 29, further comprising:

reordering third portions of data received from said R interfaces in an order transmitted by said M interfaces; and

storing said third portions for communicating said third portions to said devices.

31. The method of claim 30 further comprising:

adding sequence identifiers to portions of data transmitted by said M interfaces when M>

1; and

reordering said portions received by said R interfaces based on said sequence identifiers.