Hierarchical presentation techniques for a design tool

• US 7,712,050 B2
• Filed: 09/08/2006
• Issued: 05/04/2010
• Est. Priority Date: 04/20/2001
• Status: Expired due to Term

• Current Assignee: Siemens Industry Software Inc. (Siemens AG)
• Original Assignee: Mentor Graphics Corporation (Siemens AG)
• Inventors: Gutberlet, Peter Pius, Bowyer, Bryan Darrell, Waters, Simon Joshua
• Primary Examiner(s): BONSHOCK, DENNIS G
• Application Number:
  US11/517,638
• Publication Number:
  US 20070006112A1
• Time in Patent Office: 1,334 Days
• Field of Search: 715/963, 715/853, 705/8, 700/100
• US Class Current: 715/853
• CPC Class Codes: G06F 30/30 Circuit design
• CPC Class Codes: G06Q 10/06312 Adjustment or analysis of established resource schedule, e.g. resource or task levelling, or dynamic rescheduling
• CPC Class Codes: G06Q 10/06313 Resource planning in a project environment
• CPC Class Codes: Y10S 715/963 Calendar or scheduling
• CPC Class Codes: Y10S 715/964 CAD or CAM, e.g. interactive design tools

Abstract

A design tool hierarchically presents information about a design with nested blocks. For example, the design tool presents scheduling information for the design in a hierarchical Gantt chart. The scheduling information includes hierarchical design schedule blocks which accurately depict the timing and scheduling of the nested blocks of the design. Each of the hierarchical design schedule blocks includes control steps numbered relative to the block. The scheduling information also includes a hierarchical list of scheduled operations for the design. The hierarchical list emphasizes which operations are associated with which nested blocks. The scheduling information further includes pseudo-operation icons that are easily differentiated from real operation icons in the hierarchical Gantt chart.

Claims

1. In a design tool used to design an electronic circuit, a method comprising:

displaying a top-level schedule, in a bar chart, for a design that includes one or more loops associated with the electronic circuit, the top-level schedule being divided into steps, where each step represents a clock cycle in a iteration of a loop, and wherein timing within the top-level schedule is presented relative to the top-level schedule; and

displaying a first loop schedule, nested within the top-level schedule, for a first loop of the one or more loops, wherein timing within the first loop schedule is independent of top-level clock timing and is presented relative to the first loop schedule, with the first loop schedule being divided into sub-steps, wherein each sub-step represents a clock cycle in an iteration of the first loop and the first loop schedule, including the sub-steps, is presented within a step of the top-level schedule.

2. The method of claim 1 further comprising:

hiding the first loop schedule responsive to a command from a designer.

3. The method of claim 1 further comprising:

displaying a textual list of scheduled operations; and

displaying an icon adjacent a first loop label in the textual list, the icon indicating whether the first loop schedule is expanded or collapsed.

4. The method of claim 1 wherein the top-level schedule includes at least one pseudo-operation icon.

5. The method of claim 1 wherein the first loop includes plural alternative branches of execution having different lengths.

6. The method of claim 1 wherein the design tool is a behavioral synthesis tool.

7. A computer-readable storage medium storing computer-executable instructions for causing a computer programmed thereby to perform the method of claim 1.

8. The method of claim 1 wherein the design tool is an electronic circuit design tool or system design tool, and wherein the design is an electronic circuit design or system design.

9. In a design tool, a method of presenting information for a design of an electronic circuit, the method comprising:

presenting a first level schedule in a bar chart for a block of a design of the electronic circuit, the block including a sub-block nested within the block of the design; and

presenting second information for the sub-block of the design, wherein timing within the block is presented as independent of timing within the sub-block, and wherein the timing within the sub-block is presented as independent of the timing within the block, the timing of both the block and sub-block being associated with the timing of the electronic circuit;

wherein the first information is divided into control steps,

wherein each control step represents a clock cycle in a block iteration;

wherein the second information is divided into sub-control steps, wherein each sub-control step represents a clock cycle in an iteration of the sub-block.

10. The method of claim 9 wherein the sub-block loop is for one of plural alternative branches of execution within the block.

11. The method of claim 9 wherein the first level schedule is a block schedule and the second level schedule is a sub-block loop schedule.

12. The method of claim 11 further comprising presenting the sub-block loop schedule in a separate window.

13. The method of claim 9 wherein the first level schedule is a block schedule and the second level schedule is an icon representing a sub-block loop schedule.

14. The method of claim 13 wherein the icon appears in a clock overhead space of a step of the block schedule.

15. The method of claim 13 wherein the icon is presented in a scheduling frame that shows allowable locations of the sub-block loop schedule within the block schedule.

16. The method of claim 9 wherein timing within the sub-block loop is presented relative to the sub-block loop.

17. The method of claim 9 wherein the control steps indicate the timing within the block and the timing within the sub-block loop, and wherein each of the block and the sub-block loop includes an independently numbered set of control steps.

18. The method of claim 9 wherein the presenting the second level schedule nests the second level schedule within the first level schedule.

19. The method of claim 9 further comprising:

presenting a list of operation labels including one or more sub-block loop operation labels indented relative to one or more block operation labels in the list.

20. The method of claim 9 further comprising:

presenting a third level schedule for a second sub-block loop of the design, wherein the timing within the block is presented as independent of timing within the second sub-block loop, and wherein the timing within the second sub-block loop is presented as independent of the timing within the block.

21. The method of claim 9 wherein the design tool is a behavioral synthesis tool.

22. A computer-readable storage medium storing computer-executable instructions for causing a computer programmed thereby to perform the method of claim 9.

23. The method of claim 9 wherein the design tool is an electronic circuit design tool or system design tool, and wherein the design is an electronic circuit design or system design.

24. The method of claim 9 wherein the timing within the block is presented as independent in that the second level schedule is presented within a single control step of the block regardless of number of control steps of the sub-block loop.

25. The method of claim 9 wherein the sub-block loop includes a sub-sub-block loop, the method further comprising presenting a third level schedule for the sub-sub-block loop, wherein the timing within the block, the timing within the sub-block loop, and the timing within the sub-sub-block loop are presented as being independent of each other.

26. In a design tool, a method comprising:

presenting a top-level schedule in a bar chart that includes one or more nested loop schedules, wherein the top-level schedule is divided into control steps, wherein each control step represents a clock cycle;

presenting plural nested loop schedules in a bar chart for a design of an electronic circuit, each of the plural nested loop schedules under a top-level schedule including;

a line of control step labels, wherein control step timing for each of the plural nested loop schedules is relative to that nested loop schedule and the control step timing for each nested loop schedule and the top-level schedule is independent of the control step timings for the other nested loop schedules and the top-level schedule, the control step timing representing one or more clock cycles in a block iteration; and

one or more lines of schedule information including at least one operation icon.

27. The method of claim 26 wherein presentation of each of the plural nested loop schedules other than the top-level schedule is in a clock overhead space of a control step of the schedule enclosing the nested loop schedule.

28. The method of claim 26 wherein presentation of each of the plural nested loop schedules expands or collapses responsive to designer input.

29. The method of claim 26 wherein the design tool is a behavioral synthesis tool.

30. The method of claim 26 wherein the design tool is an electronic circuit design tool or system design tool, and wherein the design is an electronic circuit design or system design.

31. The method of claim 26 wherein each of the at least one operation icon represents a scheduled operation.