Hierarchical presentation techniques for a design tool
First Claim
1. In a design tool used to design an electronic circuit, a method comprising:
- displaying a top-level schedule, in a bar chart, for a design that includes one or more loops associated with the electronic circuit, the top-level schedule being divided into steps, where each step represents a clock cycle in a iteration of a loop, and wherein timing within the top-level schedule is presented relative to the top-level schedule; and
displaying a first loop schedule, nested within the top-level schedule, for a first loop of the one or more loops, wherein timing within the first loop schedule is independent of top-level clock timing and is presented relative to the first loop schedule, with the first loop schedule being divided into sub-steps, wherein each sub-step represents a clock cycle in an iteration of the first loop and the first loop schedule, including the sub-steps, is presented within a step of the top-level schedule.
2 Assignments
0 Petitions
Accused Products
Abstract
A design tool hierarchically presents information about a design with nested blocks. For example, the design tool presents scheduling information for the design in a hierarchical Gantt chart. The scheduling information includes hierarchical design schedule blocks which accurately depict the timing and scheduling of the nested blocks of the design. Each of the hierarchical design schedule blocks includes control steps numbered relative to the block. The scheduling information also includes a hierarchical list of scheduled operations for the design. The hierarchical list emphasizes which operations are associated with which nested blocks. The scheduling information further includes pseudo-operation icons that are easily differentiated from real operation icons in the hierarchical Gantt chart.
-
Citations
31 Claims
-
1. In a design tool used to design an electronic circuit, a method comprising:
-
displaying a top-level schedule, in a bar chart, for a design that includes one or more loops associated with the electronic circuit, the top-level schedule being divided into steps, where each step represents a clock cycle in a iteration of a loop, and wherein timing within the top-level schedule is presented relative to the top-level schedule; and displaying a first loop schedule, nested within the top-level schedule, for a first loop of the one or more loops, wherein timing within the first loop schedule is independent of top-level clock timing and is presented relative to the first loop schedule, with the first loop schedule being divided into sub-steps, wherein each sub-step represents a clock cycle in an iteration of the first loop and the first loop schedule, including the sub-steps, is presented within a step of the top-level schedule. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
-
-
9. In a design tool, a method of presenting information for a design of an electronic circuit, the method comprising:
-
presenting a first level schedule in a bar chart for a block of a design of the electronic circuit, the block including a sub-block nested within the block of the design; and presenting second information for the sub-block of the design, wherein timing within the block is presented as independent of timing within the sub-block, and wherein the timing within the sub-block is presented as independent of the timing within the block, the timing of both the block and sub-block being associated with the timing of the electronic circuit;
wherein the first information is divided into control steps,wherein each control step represents a clock cycle in a block iteration; wherein the second information is divided into sub-control steps, wherein each sub-control step represents a clock cycle in an iteration of the sub-block. - View Dependent Claims (10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25)
-
-
26. In a design tool, a method comprising:
-
presenting a top-level schedule in a bar chart that includes one or more nested loop schedules, wherein the top-level schedule is divided into control steps, wherein each control step represents a clock cycle; presenting plural nested loop schedules in a bar chart for a design of an electronic circuit, each of the plural nested loop schedules under a top-level schedule including; a line of control step labels, wherein control step timing for each of the plural nested loop schedules is relative to that nested loop schedule and the control step timing for each nested loop schedule and the top-level schedule is independent of the control step timings for the other nested loop schedules and the top-level schedule, the control step timing representing one or more clock cycles in a block iteration; and one or more lines of schedule information including at least one operation icon. - View Dependent Claims (27, 28, 29, 30, 31)
-
Specification