Manufacturing aware design of integrated circuit layouts

• US 7,712,064 B2
• Filed: 05/20/2006
• Issued: 05/04/2010
• Est. Priority Date: 05/20/2005
• Status: Expired due to Fees

• Current Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Original Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Inventors: Scheffer, Louis K., Fujimura, Akira
• Primary Examiner(s): ROSSOSHEK, YELENA
• Application Number:
  US11/419,495
• Publication Number:
  US 20060265679A1
• Time in Patent Office: 1,445 Days
• Field of Search: 716 4- 6, 716/8, 716 10- 12
• US Class Current: 716/119
• CPC Class Codes: G03F 7/70091 Illumination settings, i.e. intensity distribution in the pupil plane or angular distribution in the field plane; On-axis or off-axis settings, e.g. annular, dipole or quadrupole settings; Partial coherence control, i.e. sigma or numerical aperture [NA]
• CPC Class Codes: G03F 7/70125 Use of illumination settings tailored to particular mask patterns details of setting means G03F7/70091
• CPC Class Codes: G03F 7/70425 Imaging strategies, e.g. for increasing throughput or resolution, printing product fields larger than the image field or compensating lithography- or non-lithography errors, e.g. proximity correction, mix-and-match, stitching or double patterning
• CPC Class Codes: G05B 2219/35028 Adapt design as function of manufacturing merits, features, for manufacturing, DFM
• CPC Class Codes: G06F 2119/18 Manufacturability analysis or optimisation for manufacturability
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36
• CPC Class Codes: Y02P 90/02 Total factory control, e.g. smart factories, flexible manufacturing systems [FMS] or integrated manufacturing systems [IMS]

Abstract

Some embodiments of the invention provide a manufacturing aware process for designing an integrated circuit (“IC”) layout. The process receives a manufacturing configuration that specifies a set of manufacturing settings for a set of machines to be used to manufacture an IC based on the IC layout. The process defines a set of design rules based on the specified manufacturing configuration. The process uses the set of design rules to design the IC layout. Some embodiments of the invention provide a design aware process for manufacturing an integrated circuit (“IC”). The process receives an IC design with an associated set of design properties. The process specifies a manufacturing configuration that specifies a set of manufacturing settings for a set of machines to be used to manufacture the IC, where the specified set of manufacturing settings are based on the set of design properties. The process manufactures the IC based on the manufacturing settings.

Claims

1. A manufacturing aware process for designing an integrated circuit (“

IC”

) layout, the process comprising;

a. receiving a manufacturing configuration that specifies a set of manufacturing settings for a set of machines to be used to manufacture an IC once the IC layout is designed, wherein the set of manufacturing settings comprises a specified first dipole lens and a second dipole lens for a first layer of the IC layout;

b. prior to designing the IC layout, defining a set of design rules based on the specified manufacturing configuration; and

c. after defining the set of design rules, designing the IC layout using the set of design rules, said designing performed by at least one computer.

2. The process of claim 1, wherein the set of manufacturing settings comprises a specified aperture setting for an illuminator.

3. The process of claim 2, wherein the set of design rules based on a specified large aperture mask specify smaller dimensional attributes for elements of the IC layout than the set of design rules based on a specified small aperture mask.

4. The process of claim 1, wherein the set of manufacturing settings comprises a specified nominal exposure.

5. The process of claim 1, wherein the set of manufacturing settings comprises a specified light wavelength for an illuminator.

6. The process of claim 5, wherein the set of design rules based on a specified shorter light wavelength specify smaller dimensional attributes for elements of the IC layout than the set of design rules based on a specified longer light wavelength.

7. The process of claim 5, wherein the set of design rules based on a specified shorter light wavelength specify a denser IC layout than the set of design rules based on a specified longer light wavelength.

8. The process of claim 6, wherein at least one of the elements is a contact.

9. The process of claim 6, wherein at least one of the elements is a route.

10. The process of claim 6, wherein at least one of the elements is a module.

11. The process of claim 1, wherein defining the set of manufacturing settings further comprises a specified first exposure and a second exposure for the first layer of the IC layout.

12. The process of claim 1, wherein the set of manufacturing settings further comprises at least one of a specified off-axis light source for the first layer of the IC layout and a specified on-axis light source for the first layer of the IC layout.

13. The process of claim 1, wherein the set of manufacturing settings comprises a specified modified annular lens for the first layer of the IC layout.

14. The process of claim 13, wherein defining the set of design rules comprises defining a narrow route in a first direction of the first layer and a wide route in a second direction of the first layer.

15. The process of claim 1, wherein the set of manufacturing settings comprises a specified first modified annular lens and a second modified annular lens for the first layer of the IC layout.

16. The process of claim 1, wherein the set of manufacturing settings comprises a specified quadrupole lens for the first layer of the IC layout.

17. The process of claim 1, wherein the set of manufacturing settings comprises a specified double dipole lens for the first layer of the IC layout.

18. The process of claim 1, wherein the specified manufacturing settings comprise specifying a stepper lens for each layer of the IC layout.

19. The process of claim 18, wherein defining the set of design rules comprises defining a first width for a first route for each layer of the IC layout based on the corresponding stepper lens.

20. A manufacturing aware process for designing an integrated circuit (“

IC”

) layout, the process comprising;

a. receiving a manufacturing configuration that specifies a set of manufacturing settings for a set of machines to be used to manufacture an IC once the IC layout is designed, wherein the set of manufacturing settings comprises a specified dipole lens for a first layer of the IC layout

b. prior to designing the IC layout, defining a set of design rules based on the specified manufacturing configuration; and

c. after defining the set of design rules, designing the IC layout using the set of design rules, said designing performed by at least one computer.

21. The process of claim 20, wherein defining the set of design rules comprises defining a narrow route in a first direction of the first layer and a wide route in a second direction of the first layer.

22. The process of claim 21, wherein the dipole lens comprises two poles that are vertically aligned, wherein the first direction is a horizontal direction.

23. The process of claim 21, wherein the dipole lens comprises two poles that are horizontally aligned, wherein the first direction is a vertical direction.

24. The process of claim 21, wherein the dipole lens comprises two poles that are 45°

diagonally aligned, wherein the first direction is a 135°

diagonal direction.

25. A computer readable medium storing a computer program that when executed by a processor performs a manufacturing aware process to design an integrated circuit (“

IC”

) layout, the computer program comprising sets of instructions for;

a. receiving a manufacturing configuration that specifies a set of manufacturing settings for a set of machines to be used to manufacture an IC once the IC layout is designed, wherein the set of manufacturing settings comprises a specified first dipole lens and a second dipole lens for a first layer of the IC layout;

b. defining, prior to designing the IC layout, a set of design rules based on the specified manufacturing configuration; and

c. designing, after defining the set of design rules, the IC layout using the set of design rules.

26. The computer readable medium of claim 25, wherein defining the set of manufacturing settings further comprises a specified first exposure and a second exposure for the first layer of the IC layout.

27. The computer readable medium of claim 25, wherein the set of manufacturing settings further comprises at least one of a specified off-axis light source for the first layer of the IC layout and a specified on-axis light source for the first layer of the IC layout.

28. A system comprising:

a processor for executing sets of instructions; and

a memory for storing a computer program for performing a manufacturing aware process to design an integrated circuit (“

IC”

) layout, the computer program comprising sets of instructions for;

a. receiving a manufacturing configuration that specifies a set of manufacturing settings for a set of machines to be used to manufacture an IC once the IC layout is designed, wherein the set of manufacturing settings comprises a specified first dipole lens and a second dipole lens of a first layer for the IC layout;

b. defining, prior to designing the IC layout, a set of design rules based on the specified manufacturing configuration; and

c. designing, after defining the set of design rules, the IC layout using the set of design rules.

29. The system of claim 28, wherein defining the set of manufacturing settings further comprises a specified first exposure and a second exposure for the first layer of the IC layout.

30. The system of claim 28, wherein the set of manufacturing settings further comprises at least one of a specified off-axis light source for the first layer of the IC layout and a specified on-axis light source for the first layer of the IC layout.

31. A computer readable medium storing a computer program that when executed by a processor performs a manufacturing aware process to design an integrated circuit (“

IC”

) layout, the computer program comprising sets of instructions for;

a. receiving a manufacturing configuration that specifies a set of manufacturing settings for a set of machines to be used to manufacture an IC once the IC layout is designed, wherein the set of manufacturing settings comprises a specified dipole lens for a first layer of the IC layout;

b. prior to designing the IC layout, defining a set of design rules based on the specified manufacturing configuration; and

c. after defining the set of design rules, designing the IC layout using the set of design rules, said designing performed by at least one computer.

32. The computer readable medium of claim 31, wherein defining the set of design rules comprises defining a narrow route in a first direction of the first layer and a wide route in a second direction of the first layer.

33. The process of claim 31, wherein the dipole lens comprises two poles that are vertically aligned, wherein the first direction is a horizontal direction.

34. A system comprising:

a processor for executing sets of instructions; and

a memory for storing a computer program for performing a manufacturing aware process to design an integrated circuit (“

IC”

) layout, the computer program comprising sets of instructions for;

a. receiving a manufacturing configuration that specifies a set of manufacturing settings for a set of machines to be used to manufacture an IC once the IC layout is designed, wherein the set of manufacturing settings comprises a specified dipole lens for a first layer of the IC layout;

b. prior to designing the IC layout, defining a set of design rules based on the specified manufacturing configuration; and

c. after defining the set of design rules, designing the IC layout using the set of design rules, said designing performed by at least one computer.

35. The system of claim 34, wherein defining the set of design rules comprises defining a narrow route in a first direction of the first layer and a wide route in a second direction of the first layer.

36. The system of claim 34, wherein the dipole lens comprises two poles that are horizontally aligned, wherein the first direction is a vertical direction.