Method for monitoring a program execution using a debug logic

• US 7,712,084 B2
• Filed: 07/20/2001
• Issued: 05/04/2010
• Est. Priority Date: 07/26/2000
• Status: Expired due to Fees

• Current Assignee: Robert Bosch GmbH
• Original Assignee: Robert Bosch GmbH
• Inventors: Schneider, Klaus, Beuten, Michael, Thomas, Martin
• Primary Examiner(s): Zhen; Wei Y
• Assistant Examiner(s): Coyer; Ryan D
• Application Number:
  US09/910,206
• Publication Number:
  US 20020073400A1
• Time in Patent Office: 3,210 Days
• Field of Search: 717124-129, 717/131, 714/55, 714/10, 714 30- 39, 701/115, 365/201
• US Class Current: 717/129
• CPC Class Codes: G06F 11/3636 by tracing the execution of the program

Abstract

A method for monitoring the execution of a program executable on at least one microprocessor of a micro controller using a debug logic of the micro controller, with an exception, particularly an interrupt of the program execution, being triggered by the debug logic upon access to a specific address range during the program execution time. In order to provide monitoring of the execution of a program, executable on a microprocessor, for faults, which is particularly reliable yet conserves resources as much as possible, it is suggested that the debug logic be configured by the microprocessor and that an exception routine be executed by the debug logic after an exception has been triggered during the program execution time. The debug logic is advantageously configured during the startup of the micro controller. Preferably, the micro controller is reset and started up again and the monitored program is initialized during the execution of the exception routine.

Claims

1. A computer readable medium having a program, the program performing a method for monitoring an execution of another program that is executable on at least one microprocessor of a micro controller using a debug logic of the micro controller, comprising:

causing the debug logic to trigger an exception upon access to a specific address range during a program execution time;

causing the at least one microprocessor to configure the debug logic; and

causing the debug logic to execute an exception routine after the exception is triggered during the program execution time;

wherein the access to the specific address range includes access to an illegal storage area, and

wherein the debug logic and its registers are operated in parallel to the program execution time to check a stack having the specific address range and an exception routine is set up in reaction to a break point event in the stack, so as to provide a secure stack check without using the program execution time of the microprocessor;

wherein the debug logic monitors a program run,

wherein a memory address is stored that was accessed before an occurrence of the fault in the fault memory and at least a type of a fault is stored in a fault memory, before the micro controller is reset and started up again and before the program is initialized,

wherein during the execution of the exception routine, the micro controller is reset, the micro controller is started up again, and the program is initialized,

wherein the exception corresponds to an interrupt of the execution of the program,

wherein the debug logic is configured during a startup of the micro controller,

wherein the debug logic monitors whether the program one of (i) accesses a preselectable address range of a memory during the program execution time, and (ii) accesses an address range of a stack of the micro controller beyond a preselectable maximum stack size during the program execution time, and

wherein the debug logic monitors whether an attempt is made during the program execution time to execute a code sequence of the program in a first type of memory, swapped out from the first type of memory of the micro controller into another type of memory of the microcontroller.

2. The computer readable medium according to claim 1, further comprising:

during the execution of the exception routine, resetting the micro controller, starting up the micro controller again, and initializing the program.

3. The computer readable medium according to claim 2, further comprising the step of:

storing at least a type of a fault in a fault memory before the micro controller is reset and started up again and before the program is initialized.

4. The computer readable medium according to claim 3, further comprising the step of:

storing a memory address that was accessed before an occurrence of the fault in the fault memory before the micro controller is reset and started up again and before the program is initialized.

5. A control element for a micro controller, comprising:

an arrangement for storing a program, the program being executable on at least one microprocessor to perform the following;

causing a debug logic to trigger an exception upon access to a specific address range during a program execution time,

causing the at least one microprocessor to configure the debug logic, and

causing the debug logic to execute an exception routine after the exception is triggered during the program execution time;

wherein the access to the specific address range includes-access to an illegal storage area, and

wherein the debug logic and its registers are operated in parallel to the program execution time to check a stack having the specific address range and an exception routine is set up in reaction to a break point event in the stack, so as to provide a secure stack check without using the program execution time of the microprocessor;

wherein the debug logic monitors a program run,

wherein a memory address is stored that was accessed before an occurrence of the fault in the fault memory and at least a type of a fault is stored in a fault memory, before the micro controller is reset and started up again and before the program is initialized,

wherein during the execution of the exception routine, the micro controller is reset, the micro controller is started up again, and the program is initialized,

wherein the exception corresponds to an interrupt of the execution of the program,

wherein the debug logic is configured during a startup of the micro controller,

wherein the debug logic monitors whether the program one of (i) accesses a preselectable address range of a memory during the program execution time, and (ii) accesses an address range of a stack of the micro controller beyond a preselectable maximum stack size during the program execution time, and

wherein the debug logic monitors whether an attempt is made during the program execution time to execute a code sequence of the program in a first type of memory, swapped out from the first type of memory of the micro controller into another type of memory of the microcontroller.

6. The control element according to claim 5, wherein:

the control element corresponds to one of a read-only memory and a flash memory.

7. The control element according to claim 5, wherein:

the micro controller is arranged in a motor vehicle.

8. A micro controller, comprising:

at least one microprocessor;

a debug logic, wherein;

a program is executable on the at least one microprocessor,

the debug logic monitors an execution of the program during a program execution time and triggers an exception upon access to a specific address range, and

the at least one microprocessor configures the debug logic; and

an arrangement for executing an exception routine after the exception is triggered during the program execution time;

wherein the access to the specific address range includes-access to an illegal storage area, and

wherein the debug logic and its registers are operated in parallel to the program execution time to check a stack having the specific address range and an exception routine is set up in reaction to a break point event in the stack, so as to provide a secure stack check without using the program execution time of the microprocessor;

wherein the debug logic monitors a program run,

wherein a memory address is stored that was accessed before an occurrence of the fault in the fault memory and at least a type of a fault is stored in a fault memory, before the micro controller is reset and started up again and before the program is initialized,

wherein during the execution of the exception routine, the micro controller is reset, the micro controller is started up again, and the program is initialized,

wherein the exception corresponds to an interrupt of the execution of the program,

wherein the debug logic is configured during a startup of the micro controller,

wherein the debug logic monitors whether the program one of (i) accesses a preselectable address range of a memory during the program execution time, and (ii) accesses an address range of a stack of the micro controller beyond a preselectable maximum stack size during the program execution time, and

wherein the debug logic monitors whether an attempt is made during the program execution time to execute a code sequence of the program in a first type of memory, swapped out from the first type of memory of the micro controller into another type of memory of the microcontroller.

9. The micro controller according to claim 8, wherein:

the exception corresponds to an interrupt of the execution of the program.