Method and apparatus for optimizing a gate channel

• US 7,713,758 B2
• Filed: 06/13/2007
• Issued: 05/11/2010
• Est. Priority Date: 06/13/2007
• Status: Expired due to Fees

• Current Assignee: Tokyo Electron Limited
• Original Assignee: Tokyo Electron Limited
• Inventors: Sundararajan, Radha, Chen, Lee, Yamashita, Asao, Prager, Daniel, Funk, Merritt
• Primary Examiner(s): CULBERT, ROBERTS P
• Application Number:
  US11/762,258
• Publication Number:
  US 20080311687A1
• Time in Patent Office: 1,063 Days
• Field of Search: 438/9, 438/714, 430/710, 700/121
• US Class Current: 438/9
• CPC Class Codes: H01L 21/28017 the insulator being formed after the semiconductor body, the semiconductor being silicon
• CPC Class Codes: H01L 21/32137 of silicon-containing layers
• CPC Class Codes: H01L 22/12 for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions electrical measurement of diffusions H01L22/14
• CPC Class Codes: H01L 22/20 Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

The invention can provide a method of processing a substrate using Gate-Optimization processing sequences and evaluation libraries that can include gate-etch procedures, COR-etch procedures, and evaluation procedures.

Claims

1. A method of processing a substrate using a gate-optimization procedure comprising:

creating a patterned masking layer on the substrate;

measuring one or more test structures in the patterned masking layer using a first integrated metrology (IM) procedure, the first IM procedure creating first IM procedure data comprising first real-time data for a first test structure, and wherein the first real-time data includes first critical dimension (CD) data, first sidewall angle (SWA) data, first material data, first layer data, first optical data, or first thickness data, or any combination of two or more thereof;

etching the substrate using a first gate-etch procedure and the patterned masking layer, the first gate-etch procedure being determined in real-time using the first real-time data;

measuring one or more evaluation features on an etched substrate using a second IM procedure, the second IM procedure creating second IM procedure data comprising second real-time data for at least one evaluation feature, wherein the second real-time data includes second CD data, second SWA data, second material data, second layer data, second optical data, or second thickness data, or any combination of two or more thereof;

determining first feedback data in real-time using the first real-time data, the second real-time data, or product requirement data, or any combination of two or more thereof;

updating the first gate-etch procedure using the first feedback data when the first feedback data is less than or equal to a first limit; and

post-processing the etched substrate and storing the data associated with the substrate, when the first feedback data is greater than the first limit.

2. The method of claim 1, further comprising:

establishing first CD data and first sidewall angle data for the first test structure in the patterned masking layer;

determining a first multi-input multi-output (MIMO) model for predicting layer data in an etched layer using layer data in the patterned masking layer; and

establishing first predicted CD data and first predicted sidewall angle data for a first feature formed in the etched layer using the first CD data, the first sidewall angle data, and the first MIMO model.

3. The method of claim 2, further comprising:

determining first difference data using the second CD data and the first predicted CD data;

determining second difference data using the second sidewall angle data and the first predicted sidewall angle data; and

determining the first feedback data using the first difference data and the second difference data.

4. The method of claim 1, further comprising:

determining a first multi-input multi-output (MIMO) model for predicting gate oxide thickness data and gate oxide thickness uniformity data in an etched layer using layer data in the patterned masking layer; and

establishing first predicted gate oxide thickness data using the first thickness data, first gate-etch time, and the first MIMO model.

5. The method of claim 4, further comprising:

determining first difference data using the second thickness data and the first predicted gate oxide thickness data;

determining second difference data using the second thickness data and the first thickness data; and

determining the first feedback data using the first difference data and the second difference data.

6. The method of claim 1, wherein the one or more evaluation features include Negative Channel Field Effect Transistor (nFET) structures, Positive Channel Field Effect Transistor (pFET) structures, thickness structures, or grating structures, or a combination of two or more thereof.

7. The method of claim 1, wherein first evaluation feature data comprises first gate oxide layer data, first undoped poly-Si layer data, first doped poly-Si layer data, first nitride cap layer data, first oxide layer data, or first bottom anti-reflective coating (BARC) layer data, or any combination of two or more thereof, and a second evaluation feature data comprises second gate oxide layer data, second undoped poly-Si layer data, second nitride cap layer data, second oxide layer data, or second BARC layer data, or any combination thereof.

8. The method of claim 1, wherein the first gate-etch procedure comprises an over-etch procedure that causes a thickness change in a first area of an oxide layer proximate to a gate structure, and wherein the first feedback data is established using oxide thickness data for the first area.

9. The method of claim 1, wherein the first gate-etch procedure is performed using processing pressures between approximately 35 mTorr and approximately 45 mTorr, wherein a process time for the first gate-etch procedure is between approximately 35 seconds and approximately 45 seconds, and wherein a substrate temperature is between approximately 20 degrees C. and 30 degrees C.

10. The method of claim 1, wherein the first gate-etch procedure is performed using a first process gas comprising CHF₃ and a second process gas comprising Ar, wherein a flow rate for the first process gas is between approximately 20 sccm and approximately 30 sccm, and a flow rate for the second process gas is between approximately 450 sccm and approximately 500 sccm, and wherein the first gate-etch procedure is performed using a top electrode RF power level between approximately 220 watts and approximately 280 watts, and a bottom electrode RF power level between approximately 180 watts and approximately 220 watts.

11. The method of claim 1, wherein the first gate-etch procedure is performed using a dual backside pressure, and wherein a first backside pressure is between approximately 8 Torr and 12 Torr proximate a substrate center, and a second backside pressure is between approximately 20 Torr and 30 Torr proximate a substrate edge.

12. The method of claim 1, wherein the post-processing the etched substrate comprises:

executing a chemical oxide removal (COR) process recipe, wherein exposed surfaces on the substrate are chemically treated using a process gas, wherein a solid reaction product is formed on at least one exposed surface of the substrate; and

executing a post heat treatment (PHT) process recipe, wherein the solid reaction product is evaporated, thereby trimming chemically treated exposed surface layers.

13. The method of claim 12, wherein the executing a COR process recipe comprises:

transferring the substrate into a processing element comprising a chemical treatment chamber;

positioning the substrate on a temperature controlled substrate holder mounted within the chemical treatment chamber;

altering a chamber pressure using a vacuum pumping system coupled to the chemical treatment chamber;

providing the process gas using a gas distribution system coupled to the chemical treatment chamber and configured to introduce the process gas into the chemical treatment chamber; and

controlling the chemical treatment chamber, the temperature controlled substrate holder, the vacuum pumping system, and the gas distribution system according to the COR process recipe.

14. The method of claim 12, wherein the executing a PHT process recipe comprises:

transferring the substrate into a processing element comprising a thermal treatment chamber;

positioning the substrate on a temperature controlled substrate holder mounted within the thermal treatment chamber;

altering a chamber temperature using a temperature controlled upper assembly coupled to the thermal treatment chamber;

altering a chamber pressure using a vacuum pumping system coupled to the thermal treatment chamber; and

controlling the thermal treatment chamber, the vacuum pumping system, the temperature controlled upper assembly, and the temperature controlled substrate holder according to the PHT process recipe.

15. The method of claim 12, wherein the at least one exposed surface comprises gate oxide material, oxidized material, or damaged material, or any combination of two or more thereof.

16. The method of claim 13, wherein the process gas comprises Ar, HF and NH₃, and an Ar flow rate is between approximately 60 sccm and approximately 80 sccm, a HF flow rate is between approximately 12 sccm and approximately 16 sccm, and an NH₃, flow rate is between approximately 5 sccm and approximately 9 sccm, and wherein a process gas temperature in the gas distribution system ranges from approximately 30 degrees C. to approximately 100 degrees C.

17. The method of claim 13, wherein a temperature of the temperature controlled substrate holder in the chemical treatment chamber ranges from approximately 40 degrees C. to approximately 80 degrees C., and wherein the chamber pressure ranges from approximately 1 mTorr to approximately 100 mTorr.

18. The method of claim 14, wherein a temperature of the temperature controlled substrate holder in the thermal treatment chamber ranges from approximately 100 degrees C. to approximately 150 degrees C., the thermal treatment chamber pressure ranges from approximately 1 mTorr to approximately 100 Torr, and the temperature of the thermal treatment chamber ranges from approximately 10 degrees C. to approximately 50 degrees C.

19. A method of reducing oxide damage during substrate processing, the method comprising:

measuring one or more evaluation structures on a patterned substrate, measured data including critical dimension (CD) data, sidewall angle data, material data, layer data, optical data, or thickness data, or any combination of two or more thereof;

etching the substrate using a first over-etch process recipe;

performing a first damage-assessment procedure, first damage-assessment data including first gate oxide layer data, first undoped poly-Si layer data, first doped poly-Si layer data, first nitride cap layer data, first oxide layer data, or bottom anti-reflective coating (BARC) layer data, or any combination of two or more thereof;

determining first recipe correction data using the first damage-assessment data, the measured data, or required product data, or any combination of two or more thereof;

updating the first over-etch process recipe using the first recipe correction data when the first recipe correction data is less than or equal to a first product limit; and

performing a first chemical oxide removal (COR) procedure when the first recipe correction data is greater than the first product limit.

20. A method of performing a chamber matching process using a gate-optimization procedure, the method comprising:

obtaining first real-time measurement data for a first substrate;

etching the first substrate in a first processing chamber using a first gate-etch procedure, the first gate-etch procedure being determined in real-time using the first real-time processing data, wherein first real-time processing data is established for the first substrate;

etching a second substrate in a second processing chamber using the first gate-etch procedure, wherein second real-time processing data is established for the second substrate;

obtaining first integrated metrology (IM) data for the first etched substrate;

obtaining second IM data for the second etched substrate;

establishing first feedback data for the first processing chamber using the first real-time measurement data, the first real-time processing data, or the first IM data, or any combination thereof;

establishing second feedback data for the first processing chamber using the first real-time measurement data, the second real-time processing data, or the second IM data, or any combination thereof;

establishing a first chamber matching value using the first feedback data, the second feedback data, the first IM data, or the second IM data, or any combination thereof;

etching an additional substrate in the first processing chamber using the first gate-etch procedure when the first chamber matching value is less than or equal to a first product requirement; and

updating the first gate-etch procedure when the first chamber matching value is greater than the first product requirement.