Surface mountable direct chip attach device and method including integral integrated circuit

• US 7,713,785 B1
• Filed: 02/04/2009
• Issued: 05/11/2010
• Est. Priority Date: 03/23/2006
• Status: Active Grant

• Current Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Original Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Inventors: Flint, D. Michael Jr.
• Primary Examiner(s): LE, THAO P
• Application Number:
  US12/365,876
• Time in Patent Office: 461 Days
• Field of Search: 257/E21.141, 257/E23.174, 438/113
• US Class Current: 438/113
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2924/14 Integrated circuits

Abstract

A surface mountable chip comprises a semiconductor substrate having IC devices formed thereon and also vertically exposed electrical contacts formed as part of the IC fabrication substrate. Metallization lines electrically connect the IC devices with the contacts. The inventor also contemplates wafers having electrical connection vias in place on the wafers in preparation as a product for further fabrication. A method embodiment of the invention describes methods of fabricating such surface mountable chips.

Claims

1. A method of forming a surface mountable chip having an integrally formed integrated circuit, the method comprising:

providing a semiconductor wafer having a plurality of integrated circuit areas having integrated circuit regions and edge regions, the integrated circuit areas defined by a plurality of saw streets;

forming a plurality of vias in the edge portions of the integrated circuit areas wherein at least a portion of the vias extend into the saw streets;

filling the vias with a conductive material to form electrical contacts;

fabricating integrated circuit devices in the integrated circuit regions;

electrically connecting the integrated circuits with the electrical contacts that are associated with the integrated circuits; and

singulating the wafer in the saw streets to separate the individual integrated circuit devices and expose side portions of the electrical contact.

2. A method as in claim 1 wherein forming a plurality of vias in the edge portions comprises forming vias that pass completely through the wafer.

3. A method as in claim 2 wherein filling the vias with a conductive material comprises forming a conductive seed layer in the via;

and

plating a metal material onto the seed layer to fill the via to form the electrical contacts.

4. A method as in claim 3 wherein plating the metal material onto the seed layer comprises electroless plating of the metal material.

5. A method as in claim 3 wherein plating the metal material onto the seed layer comprises electroplating of the metal material.

6. A method as in claim 2 wherein filling the vias with a conductive material comprises depositing a conductive seed layer in the via.

7. A method as in claim 2 wherein filling the vias with a conductive material to form electrical contacts further comprises forming stacked metal layers on top of the conductive material of the electrical contacts.

8. A method as in claim 7 wherein forming the stacked metal layers on top of the conductive material of the electrical contacts is accomplished during the formation of the metallization layers used in fabricating the integrated circuit devices.

9. A method as in claim 1 wherein fabricating the integrated circuit devices in the integrated circuit regions comprises fabricating the integrated circuit devices on a top surface of the wafer;

and

wherein forming a plurality of vias in the edge portions comprises forming vias that have an opening in the top surface of the wafer but do not pass completely through the wafer.

10. A method as in claim 9 further including removing a portion of the back surface of the wafer to expose a bottom surface of the electrical contacts.