Method of forming high density trench FET with integrated Schottky diode

• US 7,713,822 B2
• Filed: 10/10/2008
• Issued: 05/11/2010
• Est. Priority Date: 03/24/2006
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Inventors: Challa, Ashok, Thorup, Paul, Marchant, Bruce Douglas
• Primary Examiner(s): Nguyen; Dao H
• Application Number:
  US12/249,889
• Publication Number:
  US 20090035900A1
• Time in Patent Office: 578 Days
• Field of Search: 438/268, 438/270, 438/273, 438/274, 257/328, 257/330, 257/E21.418, 257/E21.419
• US Class Current: 438/270
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7806 the other device being a Schottky barrier diode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A method of forming a monolithically integrated trench FET and Schottky diode includes the following steps. Two trenches are formed extending through an upper silicon layer and terminating within a lower silicon layer. The upper and lower silicon layers have a first conductivity type. First and second silicon regions of a second conductivity type are formed in the upper silicon layer between the pair of trenches. A third silicon region of the first conductivity type is formed extending into the first and second silicon regions between the pair of trenches such that remaining lower portions of the first and second silicon regions form two body regions separated by a portion of the upper silicon layer. A silicon etch is performed to form a contact opening extending through the first silicon region such that outer portions of the first silicon region remain, the outer portions forming source regions. An interconnect layer is formed filling the contact opening so as to electrically contact the source regions and the portion of the upper silicon layer. The interconnect layer electrically contacts the second silicon region so as to form a Schottky contact therebetween.

Claims

1. A method of forming a monolithically integrated trench FET and Schottky diode, the method comprising:

forming a pair of trenches extending through an upper silicon layer and terminating within a lower silicon layer, the upper and lower silicon layers having a first conductivity type, the upper silicon layer extending over the lower silicon layer;

forming first and second silicon regions of a second conductivity type in the upper silicon layer between the pair of trenches;

forming a third silicon region of the first conductivity type extending into the first and second silicon regions between the pair of trenches such that remaining lower portions of the first and second silicon regions form two body regions separated by a portion of the upper silicon layer;

performing a silicon etch to form a contact opening extending through the third silicon region such that outer portions of the third silicon region remain, the outer portions of the third silicon region forming source regions; and

forming an interconnect layer filling the contact opening so as to electrically contact the source regions and the portion of the upper silicon layer, the interconnect layer forming a Schottky contact with the portion of the upper silicon.

2. The method of claim 1 wherein the lower silicon layer has a higher doping concentration that the upper silicon layer.

3. The method of claim 1 wherein the electrical contact between the interconnect layer and the portion of the upper silicon layer is made at a depth below the source regions.

4. The method of claim 1 wherein the electrical contact between the interconnect layer and the portion of the upper silicon layer is made at a depth along a bottom half of the body regions.

5. The method of claim 1 wherein each of the first and second regions has a substantially uniform doping concentration.

6. The method of claim 1 wherein the lower silicon layer is epitaxially formed over a substrate of the first conductivity type, and the upper silicon layer is epitaxially formed over the lower silicon layer, wherein the substrate has a higher doping concentration than the lower silicon layer, and the lower silicon layer has a higher doping concentration than the upper silicon layer.

7. The method of claim 1 wherein the two body regions and the source regions are self-aligned to the pair of trenches.

8. The method of claim 1 further comprising

forming a heavy body region of the second conductivity type between the pair of trenches, the heavy body region extending into the two body regions and into the portion of the upper silicon layer, the heavy body region having a higher doping concentration than the two body regions.

9. The method of claim 8 wherein the two body regions, the source regions, and the heavy body region are self-aligned to the pair of trenches.

10. The method of claim 1 wherein the two body regions and the upper silicon layer have substantially the same depth.

11. The method of claim 1 further comprising:

forming a recessed gate electrode in each trench; and

forming a dielectric cap insulating each gate electrode from the interconnect layer.

12. The method of claim 11 further comprising:

before forming the recessed gate electrode, forming a shield electrode in a bottom portion of each trench.

13. The method of claim 11 further comprising:

before forming the recessed gate, forming a thick bottom dielectric extending along a bottom of each trench.

14. The method of claim 1 wherein the interconnect layer is a Schottky barrier metal layer.

15. A method of forming a monolithically integrated trench MOSFET and Schottky diode, the method comprising:

using a mask, forming a first plurality of trenches extending into and terminating in an upper silicon layer, the upper silicon layer extending over a lower silicon layer, the upper and lower silicon layers having a first conductivity type;

filling the first plurality of trenches with silicon material of a second conductivity type;

performing a thermal cycle to diffuse out the silicon material into the upper silicon layer and under the mask;

using the mask, forming a second plurality of trenches extending through the silicon material, the upper silicon layer, and terminating within the lower silicon layer such that the diffused out portions of the silicon material under the mask remain on each side of corresponding trenches;

forming a first silicon region of the first conductivity type extending into the diffused out portions such that remaining lower portions of the diffused out portions between every two adjacent trenches form two body regions separated by a portion of the upper silicon layer;

performing a silicon etch to form a contact opening extending through the first silicon region such that outer portions of the first silicon region remain, the outer portions of the first silicon region forming source regions; and

forming an interconnect layer filling the contact opening so as to electrically contact the source regions and the portion of the upper silicon layer, the interconnect layer forming a Schottky contact with the portion of the upper silicon.

16. A method of forming a monolithically integrated trench MOSFET and Schottky diode, the method comprising:

using a mask, forming a plurality of trenches extending through an upper silicon layer and terminating within a lower silicon layer, the upper and lower silicon layers having a first conductivity type, the upper silicon layer extending over the lower silicon layer;

performing a two-pass angled implant to form first silicon regions of a second conductivity type in the upper silicon layer along upper sidewalls of each trench;

forming a second silicon region of the first conductivity type extending into the first silicon regions between every two adjacent trench such that remaining lower portions of the first silicon regions form two body regions between every two adjacent trenches, the two body regions being separated by a portion of the upper silicon layer;

performing a silicon etch to form a contact opening extending through the second silicon region such that outer portions of the second silicon region remain between every two adjacent trenches, the outer portions of the second silicon region forming source regions; and

forming an interconnect layer filling the contact opening so as to electrically contact the source regions and the portion of the upper silicon layer, the interconnect layer forming a Schottky contact with the portion of the upper silicon.

17. The method of claim 16 wherein regions of the upper silicon layer which receive dopants during the two-pass angled implant are defined by the implant angle and a thickness of the mask.

18. A method of forming a monolithically integrated trench MOSFET and Schottky diode, the method comprising:

using a mask, forming a first plurality of trenches extending into and terminating at a first depth within an upper silicon layer, the upper silicon layer extending over a lower silicon layer, the upper and lower silicon layers having a first conductivity type;

performing a two-pass angled implant to form first silicon regions of a second conductivity type in the upper silicon layer along sidewalls of each trench;

using the mask, extending the plurality of trenches deeper to a second depth with the lower silicon layer;

forming a second silicon region of the first conductivity type extending into the first silicon regions between every two adjacent trench such that remaining lower portions of the first silicon regions form two body regions between every two adjacent trenches, the two body regions being separated by a portion of the upper silicon layer;

performing a silicon etch to form a contact opening extending through the second silicon region such that outer portions of the second silicon region remain between every two adjacent trenches, the outer portions of the second silicon region forming source regions; and

forming an interconnect layer filling the contact opening so as to electrically contact the source regions and the portion of the upper silicon layer, the interconnect layer forming a Schottky contact with the portion of the upper silicon.

19. The method of claim 18 wherein regions of the upper silicon layer which receive dopants during the two-pass angled implant are defined by the first depth of the plurality of trenches, a thickness of the mask, and the implant angle.