Integrated circuits and methods of manufacturing thereof

• US 7,714,377 B2
• Filed: 04/19/2007
• Issued: 05/11/2010
• Est. Priority Date: 04/19/2007
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Qimonda AG (Infineon Technologies AG), Qimonda Flash GmbH (Infineon Technologies AG)
• Inventors: Specht, Michael, Nagel, Nicolas, Hofmann, Franz, Mikolajick, Thomas
• Primary Examiner(s): Tran; Thien F
• Application Number:
  US11/737,617
• Publication Number:
  US 20080259687A1
• Time in Patent Office: 1,118 Days
• Field of Search: 257315-317, 257/321, 257/324
• US Class Current: 257/316
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 41/35 with a cell select transistor, e.g. NAND
• CPC Class Codes: H10B 43/30 characterised by the memory core region
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
• CPC Class Codes: Y10T 29/49117 Conductor or circuit manufacturing

Abstract

Embodiments of the invention relate to integrated circuits having a memory cell arrangement and methods of manufacturing thereof. In one embodiment of the invention, an integrated circuit has a memory cell arrangement which includes a fin structure extending in its longitudinal direction as a first direction, including a first insulating layer, a first active region disposed above the first insulating layer, a second insulating layer disposed above the first active region, a second active region disposed above the second insulating layer, a charge storage layer structure disposed at least next to at least one sidewall of the fin structure covering at least a portion of the first active region and at least a portion of the second active region, and a control gate disposed next to the charge storage layer structure.

Claims

1. An integrated circuit having a memory cell arrangement, the memory cell arrangement comprising:

a fin structure extending in a longitudinal direction as a first direction, the fin structure comprising;

a first insulating layer;

a first active region disposed above the first insulating layer;

a second insulating layer disposed above the first active region; and

a second active region disposed above the second insulating layer;

a charge storage layer structure disposed adjacent at least one sidewall of the fin structure covering at least a portion of the first active region and at least a portion of the second active region; and

a control gate disposed adjacent the charge storage layer structure.

2. The integrated circuit of claim 1, wherein the fin structure further comprises:

a third insulating layer disposed above the second active region; and

a third active region disposed above the third insulating layer.

3. The integrated circuit of claim 1, wherein the fin structure comprises at least one additional first active region and at least one additional second active region,

the first active region and the at least one additional first active region being coupled with each other in a serial connection in the first direction,

the second active region and the at least one additional second active region being coupled with each other in serial connection in the first direction.

4. The integrated circuit of claim 3, further comprising:

at least one additional charge storage layer structure disposed above at least a portion of the at least one additional first active region and at least a portion of the at least one additional second active region in a second direction; and

at least one additional control gate disposed above the at least one additional charge storage layer structure in the second direction.

5. The integrated circuit of claim 1, further comprising source/drain regions adjacent the first active region and the second active region.

6. The integrated circuit of claim 1, wherein the fin structure further comprises source/drain regions adjacent the first active region and the second active region.

7. The integrated circuit of claim 1, wherein the charge storage layer structure comprises a floating gate layer structure.

8. The integrated circuit of claim 1, wherein the charge storage layer structure comprises a nanocrystalline type layer structure comprising nanocrystals embedded in a dielectric, the nanocrystals storing electrical charges.

9. The integrated circuit of claim 1, wherein the charge storage layer structure comprises a charge trapping layer structure.

10. The integrated circuit of claim 9, wherein the charge trapping layer structure comprises at least two dielectric layers.

11. The integrated circuit of claim 9, wherein the charge trapping layer structure comprises a charge trapping layer comprising a material selected from the group consisting of silicon nitride, yttrium oxide, hafnium oxide, zirconium oxide, a hafnium silicate, a hafnium aluminate, aluminum nitride, and aluminum oxide.

12. The integrated circuit of claim 9, wherein the charge trapping layer structure comprises an oxide/nitride/oxide layer stack.

13. The integrated circuit of claim 12, wherein a bottommost oxide layer of the oxide/nitride/oxide layer stack comprises silicon oxide, or one or more high-k-material layers containing silicon oxide.

14. The integrated circuit of claim 12, wherein an uppermost oxide layer of the oxide/nitride/oxide layer stack comprises one or more materials selected from the group of materials consisting of silicon oxide, aluminum oxide, high-k-material, mixtures of those materials, silicates of those materials, aluminates of those materials, silicon nitride, yttrium oxide, hafnium oxide, zirconium oxide, hafnium silicates, hafnium aluminates, aluminum nitride, and aluminum oxide.

15. The integrated circuit of claim 1, further comprising a select unit individually selecting sectors of memory cell transistors formed by the first active region and the second active region.

16. The integrated circuit of claim 15, wherein the select unit is formed in the fin structure.

17. The integrated circuit of claim 15, wherein the select unit comprises a plurality of select lines.

18. The integrated circuit of claim 17, further comprising:

a further fin structure extending in a longitudinal direction as a first direction, the further fin structure comprising;

a first insulating layer;

a first active region disposed above the first insulating layer;

a second insulating layer disposed above the first active region; and

a second active region disposed above the second insulating layer;

a charge storage layer structure disposed adjacent at least one sidewall of the fin structure, the charge storage layer covering, at least a portion of the first active region and at least a portion of the second active region; and

a control gate disposed adjacent the charge storage layer.

19. The integrated circuit of claim 18, wherein the select unit is coupled between the fin structure and the further fin structure.

20. The integrated circuit of claim 17, wherein the plurality of select lines are arranged in a switch matrix.

21. The integrated circuit of claim 20, wherein:

some of the plurality of select lines comprise normally-off select transistors; and

others of the plurality of select lines comprise normally-on select transistors.

22. The integrated circuit of claim 21, wherein the number of select lines comprising normally-on transistors in the switch matrix is equal to the number of active regions that are disposed above one another in the fin structure.

23. The integrated circuit of claim 21, wherein the total number of select lines in the switch matrix between a bit line contact and memory cell transistors is equal to the number of active regions disposed above one another in the fin structure or is greater by one than the number of active regions disposed above one another in the fin structure.

24. The integrated circuit of claim 21, wherein at least some of the normally-off transistors are doped with heavy ions.

25. The integrated circuit of claim 24, where at least some of the normally-off transistors are doped with indium or boron fluoride.

26. The integrated circuit of claim 20, wherein the switch matrix further comprises a bit line contact region coupling each of the memory cell transistors of the first active region and the second active region via the select lines.

27. The integrated circuit of claim 26, wherein at least one of the transistors of the switch matrix has a greater gate length than all other transistors of the switch matrix.

28. An integrated circuit having a NAND memory cell arrangement, the integrated circuit comprising:

a fin structure extending in a first direction, comprising;

a first insulating layer;

a plurality of first active regions of a first plurality of memory cells being coupled with each other in serial connection in the first direction and being disposed above the first insulating layer;

a second insulating layer disposed above the first active regions; and

a plurality of second active regions of a second plurality of memory cells being coupled with each other in serial connection in the first direction and being disposed above the second insulating layer;

a plurality of charge storage layer structures disposed adjacent at least one sidewall of the fin structure covering at least a portion of the first active region and at least a portion of the second active region; and

a plurality of control gate layers disposed next to the charge storage layer structures;

the memory cells being coupled with each other to form a first plurality of NAND coupled memory cells comprising the plurality of first active regions, and a second plurality of NAND coupled memory cells comprising the plurality of second active regions.

29. The integrated circuit of claim 28, further comprising a select unit individually selecting one sector of the plurality of memory cells formed by the first active region and the second active region.

30. The integrated circuit of claim 29, wherein the select unit is formed in the fin structure.

31. An integrated circuit having a NAND memory cell arrangement, the integrated circuit comprising:

a fin structure extending a first direction, the fin structure comprising;

a first insulating layer;

a plurality of first active regions of a first plurality of memory cells coupled with each other in serial connection in the first direction and disposed above the first insulating layer;

a second insulating layer disposed above the first active regions; and

a plurality of second active regions of a second plurality of memory cells coupled with each other in serial connection in the first direction and disposed above the second insulating layer;

a plurality of charge storage layers disposed adjacent at least one sidewall of the fin structure covering at least a portion of the first active region and at least a portion of the second active region;

a plurality of control gate layers disposed next to the charge storage layer, the control gate layers being coupled with each other to form a first plurality of NAND coupled memory cells comprising the plurality of first active regions, and a second plurality of NAND coupled memory cells comprising the plurality of second active regions; and

a switch arrangement comprising switches individually selecting the memory cells.

32. The integrated circuit of claim 31, wherein the switch arrangement being formed in the fin structure.

33. An integrated circuit having a memory cell arrangement, comprising:

a plurality of memory cells arranged above one another in a fin structure; and

a switching structure including switching elements, at least some of the switching elements being arranged above one another, each switching element being assigned to a respective memory cell.

34. A memory module, comprising:

a plurality of integrated circuits, wherein at least one integrated circuit of the plurality of integrated circuits comprises a memory cell arrangement, the memory cell arrangement comprising;

a fin structure extending a first direction, the fin structure comprising;

a first insulating layer;

a first active region disposed above the first insulating layer;

a second insulating layer disposed above the first active region; and

a second active region disposed above the second insulating layer;

a charge storage layer structure adjacent at least one sidewall of the fin structure covering at least a portion of the first active region and at least a portion of the second active region; and

a control gate adjacent the charge storage layer.

35. The memory module of claim 34, wherein the memory module is a stackable memory module in which at least some of the integrated circuits are stacked one above the other.