Nonvolatile semiconductor integrated circuit devices and fabrication methods thereof

• US 7,714,378 B2
• Filed: 07/17/2006
• Issued: 05/11/2010
• Est. Priority Date: 08/09/2005
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Choi, Jeong-hyuk, Kim, Tae-kyung
• Primary Examiner(s): Smith; Matthew
• Assistant Examiner(s): Jefferson; Quovaunda
• Application Number:
  US11/487,834
• Publication Number:
  US 20070034955A1
• Time in Patent Office: 1,394 Days
• Field of Search: 257314-316, 257/319, 257/324, 257349-351, 257/320, 257/E29.129, 257/E29.13, 257/390, 257/E29.158, 257/E21.179
• US Class Current: 257/319
• CPC Class Codes: H01L 21/76804 by forming tapered via holes
• CPC Class Codes: H01L 21/76834 formation of thin insulating films on the sidewalls or on top of conductors H01L21/76831 takes precedence
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: H10B 41/10 characterised by the top-view layout
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 41/35 with a cell select transistor, e.g. NAND
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

In a method for manufacturing a semiconductor device, an oxide layer, a first polysilicon layer, and a second polysilicon layer are sequentially provided on a substrate. A first hard mask pattern is provided on the second polysilicon layer. The oxide layer, the first polysilicon layer, and the second polysilicon layer are patterned using the first hard mask pattern as a mask to form a lower gate structure including an oxide pattern, a first polysilicon pattern, and a second polysilicon pattern. The lower gate structure is etched to provide an oxidation layer on sidewalls of the lower gate structure. An insulating layer is provided on the lower gate structure including the oxidation layer. The first hard mask pattern is removed to form a first opening in the insulating layer, the first opening exposing the second polysilicon pattern. A metal pattern is formed in the first opening on the second polysilicon pattern, the second polysilicon pattern having the oxidation layer on sidewalls thereof.

Claims

1. A semiconductor device comprising:

a semiconductor substrate;

multiple floating gate structures, each comprising;

a tunnel oxide layer pattern on the substrate;

a floating gate polysilicon layer pattern on the tunnel oxide layer pattern;

an inter-gate dielectric layer pattern on the floating gate polysilicon layer pattern;

a control gate polysilicon layer pattern on the inter-gate dielectric layer pattern;

a control gate metal layer pattern on the control gate polysilicon layer pattern, wherein a width of the control gate metal layer pattern is greater than a width of the control gate polysilicon layer pattern; and

a hard mask pattern on the control gate metal layer pattern, wherein a lower side of the hard mask pattern contacts the control gate metal layer pattern and a width of the lower side of the hard mask pattern is greater than a width of the control gate metal layer pattern;

an insulating layer on the substrate and on the multiple floating gate structures; and

an inter-layer contact in the insulating layer between a pair of the multiple floating gate structures, wherein the inter-layer contact has an upper portion that is wider than a lower portion thereof, and wherein the upper portion of the inter-layer contact overlaps a portion of the control gate metal layer pattern.

2. The semiconductor device of claim 1 wherein the tunnel oxide layer pattern, the floating gate polysilicon layer pattern, the inter-gate dielectric layer pattern, the control gate polysilicon layer pattern and the control gate metal layer pattern comprise a floating gate structure and wherein the floating gate structure is on an active region of the semiconductor substrate, and wherein source and drain regions are in the semiconductor substrate adjacent sidewalls of the floating gate structure.

3. The semiconductor device of claim 1 wherein the control gate metal layer patterns of adjacent floating gate structures are connected to provide one of word lines and bit lines of the semiconductor device.

4. The semiconductor device of claim 1 wherein the hard mask pattern is used for self-alignment of the inter-layer contact.

5. A semiconductor device comprising:

a semiconductor substrate;

multiple gate structures, each comprising;

a tunnel oxide layer pattern on the substrate;

a first polysilicon layer pattern on the tunnel oxide layer pattern;

a second polysilicon layer pattern on the first polysilicon layer pattern;

a metal layer pattern on the second polysilicon layer pattern; and

a hard mask pattern on the metal layer pattern, wherein a lower side of the hard mask pattern contacts the metal layer pattern and a width of the lower side of the hard mask pattern is greater than a width of the metal layer pattern;

an insulating layer on the substrate and on the multiple gate structures; and

an inter-layer contact in the insulating layer between a pair of the multiple gate structures, wherein the inter-layer contact has an upper portion that is wider than a lower portion thereof, and wherein the upper portion of the inter-layer contact overlaps a portion of the metal layer pattern, and

wherein the hard mask pattern is used for self-alignment of the inter-layer contact.

6. The semiconductor device of claim 5 wherein the first polysilicon layer pattern has a dopant concentration that is different than the second polysilicon layer pattern.

7. The semiconductor device of claim 5 further comprising an inter-gate dielectric layer pattern on the first polysilicon layer pattern, and wherein the semiconductor device comprises a floating gate device.

8. The semiconductor device of claim 5 wherein the semiconductor device comprises a field effect transistor.

9. The semiconductor device of claim 5 further comprising source and drain regions in the semiconductor substrate adjacent sidewalls of the gate structures.

10. The semiconductor device of claim 5 wherein the metal layer patterns of adjacent gate structures are connected to provide one of word lines, bit lines, and transistor selection lines of the semiconductor device.

11. A semiconductor device comprising:

a semiconductor substrate;

multiple gate structures, each comprising;

a tunnel oxide layer pattern on the substrate;

a first polysilicon layer pattern on the tunnel oxide layer pattern;

a second polysilicon layer pattern on the first polysilicon layer pattern;

a metal layer pattern on the second polysilicon layer pattern, wherein a width of the metal layer pattern is greater than a width of the second polysilicon layer pattern; and

a hard mask pattern on the metal layer pattern, wherein a lower side of the hard mask pattern contacts the metal layer pattern and a width of the lower side of the hard mask pattern is greater than a width of the metal layer pattern;

an insulating layer on the substrate and on the multiple gate structures; and

an inter-layer contact in the insulating layer between a pair of the multiple gate structures, wherein the hard mask pattern is used for self-alignment of the inter-layer contact, and wherein the inter-layer contact has an upper portion that is wider than a lower portion thereof, and wherein the upper portion of the inter-layer contact overlaps a portion of the metal layer pattern.