Dynamic random access memory with an electrostatic discharge structure and method for manufacturing the same

• US 7,714,445 B2
• Filed: 12/05/2007
• Issued: 05/11/2010
• Est. Priority Date: 07/11/2007
• Status: Active Grant

• Current Assignee: Nanya Technology Corporation
• Original Assignee: Nanya Technology Corporation
• Inventors: Chuang, Ying-Cheng, Chiu, Shih-Yang, Hsiao, Ching-Nan, Huang, Chung-Lin
• Primary Examiner(s): Andújar; Leonardo
• Assistant Examiner(s): HARRISTON, WILLIAM A
• Application Number:
  US11/951,274
• Publication Number:
  US 20090014886A1
• Time in Patent Office: 888 Days
• Field of Search: 438/241, 438/258, 438/682, 438/396, 438/586, 438/970, 438/592, 257/774, 257/E21.649
• US Class Current: 257/774
• CPC Class Codes: H01L 27/0251 for MOS devices
• CPC Class Codes: H10B 12/09 with simultaneous manufacture of the peripheral circuit region and memory cells

Abstract

The invention provides a dynamic random access memory (DRAM) with an electrostatic discharge (ESD) region. The upper portion of the ESD plug is metal, and the lower portion of the ESD plug is polysilicon. This structure may improve the mechanical strength of the ESD region and enhance thermal conductivity from electrostatic discharging. In addition, the contact area between the ESD plugs and the substrate can be reduced without increasing aspect ratio of the ESD plugs. The described structure is completed by a low critical dimension controlled patterned photoresist, such that the processes and equipments are substantially maintained without changing by a wide margin.

Claims

1. A method for manufacturing an electrostatic discharge structure, comprising the steps of:

providing a substrate having an electrostatic discharge region, wherein the electrostatic discharge region has a plurality of conductive structures;

forming a patterned, conductive sacrificial layer on the substrate between two adjacent conductive structures;

forming an interlayer dielectric layer over the substrate, wherein the interlayer dielectric layer encompasses the patterned, conductive sacrificial layer and exposes a top surface of the patterned, conductive sacrificial layer;

partially removing the patterned, conductive sacrificial layer to form a lower portion of a plug; and

filling a conductor into a contact hole wherein the conductor constitutes an upper portion of the plug to directly and electrically connected to the lower portion.

2. The method as claimed in claim 1 further comprising forming a collar insulator between the patterned, conductive sacrificial layer and the interlayer dielectric layer.

3. The method as claimed in claim 1, wherein each of the conductive structures comprises a gate dielectric layer, a metal silicide layer, a polysilicon layer, and a hard mask layer sequentially stacked on the substrate.

4. The method as claimed in claim 1 further comprising forming an insulating mask pattern situated directly under the patterned, conductive sacrificial layer, wherein the insulating mask pattern has an opening that defines a shrunk contact area of the plug.

5. An electrostatic discharge structure, comprising:

a substrate having a plurality of conductive structures thereon;

an interlayer dielectric layer formed on the substrate, wherein the interlayer dielectric layer has a contact hole between the conductive structures;

a bi-layer plug embedded in the contact hole;

an insulating mask pattern situated directly under the bi-layer plug, wherein the insulating mask pattern has an opening that defines a contact area of the bi-layer plug to the substrate.

6. The electrostatic discharge structure as claimed in claim 5, wherein the bi-layer plug comprises a polysilicon lower portion and a metal upper portion, and wherein the polysilicon lower portion fills into the opening.

7. The electrostatic discharge structure as claimed in claim 6 further comprising a collar insulator between the bi-layer plug and the interlayer dielectric layer.