Low noise voltage reference circuit

• US 7,714,563 B2
• Filed: 03/13/2007
• Issued: 05/11/2010
• Est. Priority Date: 03/13/2007
• Status: Active Grant

• Current Assignee: Analog Devices, Inc.
• Original Assignee: Analog Devices, Inc.
• Inventors: Marinca, Stefan
• Primary Examiner(s): BEHM, HARRY RAYMOND
• Application Number:
  US11/717,516
• Publication Number:
  US 20080224759A1
• Time in Patent Office: 1,155 Days
• Field of Search: 323/316, 323/313, 323/314, 323/317, 323/315, 327/539
• US Class Current: 323/316
• CPC Class Codes: G05F 3/30 Regulators using the difference between the base-emitter voltages of two bipolar transistors operating at different current densities G05F3/26 takes precedence

Abstract

A low noise voltage reference circuit is described. The reference circuit utilizes a bandgap reference component and may include at least one of a current shunt or filter to reduce high and low noise contributions to the output. Further modifications may include a curvature correction component.

Claims

1. A bandgap reference circuit including an amplifier having an inverting and a non-inverting input and providing at its output a voltage reference, the circuit including:

a. a first pair of transistors, the first pair including a first and second transistor of the circuit, the first transistor being coupled to the non-inverting input of the amplifier, the bases of the first and second transistors being commonly coupled, the first transistor being additionally coupled to the amplifier output via a feedback resistor, the second transistor being provided in a diode configuration,

b. a second pair of transistors, the second pair including a third and fourth transistor of the circuit, the third transistor being coupled to the inverting input of the amplifier, the emitters of the third and fourth transistors being coupled to ground via a reference resistor, the fourth transistor being provided in a diode configuration and being coupled via a coupling resistor to the second transistor, and

wherein the base of the third transistor is coupled to the commonly coupled first and second transistors, the collector of the third transistor being coupled to the collector of the first transistor such that the first and third transistors form a preamplifier to the amplifier, and further wherein the emitter areas of the first and fourth transistors are scaled to be larger than that the emitter areas of the second and third transistors such that two base-emitter voltage differences, of the form of proportional to absolute temperature (PTAT) voltages, are developed across the coupling and feedback resistors respectively, the resultant PTAT currents generating a PTAT voltage across the reference resistor, this PTAT voltage in combination with the base emitter voltages of the combined second and third transistors being reflected at the output of the amplifier as a first order temperature insensitive voltage, and further wherein the circuit includes a filter provided between the non-inverting input and ground to minimize high band noise contributions to said temperature insensitive voltage, the circuit further including;

a current shunt provided to shunt at least a portion of the feedback current away from the first transistor so as to effect a reduction in the collector and base currents of the first and third transistors thereby reducing low band noise contributions to said temperature insensitive voltage.

2. The circuit as claimed in claim 1 wherein the current shunt is configured to reduce the collector current of the first and third transistors and as a result to effect a reduction in the base currents of the first and third transistors.

3. The circuit as claimed in claim 2 wherein the current shunt includes two npn transistors and one pnp transistor, the pnp transistor forming a fifth transistor of the circuit, the two npn transistors forming sixth and seventh transistors of the circuit.

4. The circuit of claim 3 wherein the emitter areas of the transistors are chosen such that the second and third transistors have a first emitter area, n, the fourth transistor has a second emitter area n1, the first transistor has a third emitter area, n2, the fifth transistor has a fourth emitter area, n3, the sixth transistor has a fifth emitter area, n4 and the seventh transistor has a sixth emitter area, n5, the emitter areas being scaled such that n5>

n4>

n3>

n2>

n1>

n.

5. The circuit of claim 1 wherein the filter includes a capacitor.

6. The circuit of claim 5 wherein the capacitor has a value less than 1000 pF.

7. The circuit of claim 6 wherein the capacitor has a value less than 200 pF.

8. The circuit of claim 6 wherein the capacitor has a value of about 100 pF.

9. The circuit of claim 1 further including a curvature correction component.

10. The circuit of claim 9 wherein the curvature correction component is configured to provide a correction voltage of the type TlogT of opposite sign to that of the first order voltage reference voltage output, the correction voltage being combined with the first order voltage reference to provide a curvature corrected voltage reference.

11. A bandgap reference circuit including an amplifier having an inverting and a non-inverting input and providing at its output a voltage reference, the circuit including:

a. a first pair of transistors of a first type the first pair including a first and second transistor of the circuit, the first transistor being coupled to the non-inverting input of the amplifier, the bases of the first and second transistors being commonly coupled, the first transistor being additionally coupled to the amplifier output via a feedback resistor, the second transistor being provided in a diode configuration,

b. a second pair of transistors of a second type, the second pair including a third and fourth transistor of the circuit, the third transistor being coupled to the inverting input of the amplifier, the emitters of the third and fourth transistors being coupled to ground via a reference resistor, the fourth transistor being provided in a diode configuration and being coupled via a coupling resistor to the second transistor, and

wherein the base of the third transistor is coupled to the commonly coupled first and second transistors, the collector of the third transistor being coupled to the collector of the first transistor such that the first and third transistors form a preamplifier to the amplifier, and further wherein the emitter areas of the first and fourth transistors are scaled to be larger than the emitter areas of the second and third transistors such that two base-emitter voltage differences, of the form of proportional to absolute temperature (PTAT) voltages, are developed across the coupling and feedback resistors respectively, the resultant PTAT currents generating a PTAT voltage across the reference resistor, this PTAT voltage in combination with the base emitter voltages of the combined second and third transistors being reflected at the output of the amplifier as a first order temperature-insensitive voltage, and further wherein the circuit includes a current shunt configured to shunt at least a portion of the feedback current away from the first transistor so as to effect a reduction in the collector and base currents of the first and third transistors thereby reducing low band noise contributions to said this temperature-insensitive voltage.

12. The circuit as claimed in claim 11 wherein the current shunt is configured to reduce the collector current of the first and third transistors and as a result to effect a reduction in the base currents of the first and third transistors.

13. The circuit as claimed in claim 12 wherein the current shunt includes two npn transistors and on pnp transistor, the pnp transistor forming a fifth transistor of the circuit, the two npn transistors forming sixth and seventh transistors of the circuit.

14. The circuit of claim 13 wherein the emitter areas of the transistors are chosen such that the second and third transistors have a first emitter area, n, the fourth transistor has a second emitter area n1, the first transistor has a third emitter area, n2, the fifth transistor has a fourth emitter area, n3, the sixth transistor has a fifth emitter area, n4 and the seventh transistor has a sixth emitter area, n5, the emitter areas being scaled such that n5>

n4>

n3>

n2>

n1>

n.

15. The circuit of claim 11 further including a filter provided between the non-inverting input and ground to minimize high band noise contributions to said temperature insensitive voltage.

16. The circuit of claim 15 wherein the filter includes a capacitor.

17. The circuit claim 16 wherein the capacitor has a value less than 1000 pF.

18. The circuit of claim 16 wherein the capacitor has a value less than 200 pF.

19. The circuit of claim 18 wherein the capacitor has a value of about 100 pF.

20. The circuit of claim 11 further including a curvature correction component.

21. The circuit of claim 20 wherein the curvature correction component is configured to provide a correction voltage of the type TlogT of opposite sign to that of the first order voltage reference voltage output, the correction voltage being combined with the first order voltage reference to provide a curvature corrected voltage reference.

22. A bandgap reference circuit including an amplifier having an inverting and a non-inverting input and providing at its output a voltage reference, the circuit including:

a. a first pair of pnp transistors, the first pair including a first and second transistor of the circuit, the first transistor being coupled to the non-inverting input of the amplifier, the bases of the first and second transistors being commonly coupled, the first transistor being additionally coupled to the amplifier output via a feedback resistor, the second transistor being provided in a diode configuration,

b. a second pair of npn transistors, the second pair including a third and fourth transistor of the circuit, the third transistor being coupled to the inverting input of the amplifier, the emitters of the third and fourth transistors being coupled to ground via a reference resistor, the fourth transistors being coupled to ground via a reference resistor, the fourth transistor being provided in a diode configuration and being coupled via a coupling resistor to the second transistor, and

wherein the base of the third transistor is coupled to the commonly coupled first and second transistors, collector of the third transistor being coupled to the collector of the first transistor such that the first and third transistors form a preamplifier to the amplifier, and further wherein the emitter areas of the first and fourth transistors are scaled to be larger than that the emitter areas of the second and third transistors such that two base-emitter voltage differences, of the form of proportional to absolute temperature (PTAT) voltages, are developed across the coupling and feedback resistors respectively, the resultant PTAT currents generating a PTAT voltage across the reference resistor, this PTAT voltage in combination with the base emitter voltages of the combined second and third transistors being reflected at the output of the amplifier as a first order temperature insensitive voltage, and further wherein the circuit further includes;

a filter provided between the non-inverting input and ground to minimize high band noise contributions to said temperature insensitive voltage, and

a current shunt configured to shunt at least a portion of the feedback current away from the first transistor so as to effect a reduction in the collector and the base currents of the first and third transistors thereby reducing low band noise contributions to said temperature insensitive voltage.

23. The circuit as claimed in claim 22 wherein the current shunt is configured to reduce the collector of the first and third transistors and as a result to effect a reduction in the base currents of the first and third transistors.

24. The circuit as claimed in claim 23 wherein the current shunt includes two npn transistors and on pnp transistor, the pnp transistor forming a fifth transistor of the circuit, the two npn forming sixth and seventh transistors of the circuit.

25. The circuit of claim 24 wherein the emitter areas of the transistors are chosen such that the second and third transistors have a first emitter area, n, the fourth transistor has a second emitter area n1, the first transistor has a third emitter area, n2, the fifth transistor has a fourth emitter area, n3, the sixth transistor has a fifth emitter area, n4 and the seventh transistor has a sixth emitter area, n5, the emitter areas being scaled such that n5>

n4>

n3>

n2>

n1>

n.

26. The circuit of claim 22 wherein a capacitor has a value less than 1000 pF.

27. The circuit of claim 22 wherein the capacitor has a value less than 200 pF.

28. The circuit of claim 27 wherein the capacitor has a value of about 100 pF.

29. The circuit of claim 22 further including a curvature correction component.

30. The circuit of claim 29 wherein the curvature correction component is configured to provide a correction voltage of the type TlogT of opposite sign to that of the first order voltage reference voltage output, the correction voltage being combined with the first order voltage reference to provide a curvature corrected voltage reference.

31. The circuit of claim 22 wherein a capacitor is provided on-chip.

32. A voltage reference circuit including:

an amplifier having first and second inputs and an output,

first and second npn transistors being associated with the first and second inputs of the amplifier respectively, the base of the first npn transistor being coupled to the second input of the amplifier and the collector of the first npn transistor being coupled to the first input of the amplifier such that the amplifier keeps the base and collector of the first transistor at the same potential, the second npn transistor being provided in a diode configuration, and wherein the first and second npn transistors are adapted to operate at different current densities such that a difference in base emitter voltages between the first and second npn transistors may be generated across a resistive load coupled to the second npn transistor, the difference in base emitter voltages being a PTAT voltage,

first and second pnp transistors, the first pnp transistor being provided in a feedback configuration between the output of the amplifier and the first input of the amplifier, the second pnp transistor being provided in a diode configuration with the base and collector being commonly coupled via the resistive load to the second npn transistor and also to the second input of the amplifier, the collector of the first input of the amplifier, the arrangement of the first pnp transistor and first npn transistor providing a pre-amplification of the signal prior to the amplification provided by the amplifier, and

a current shunt configured to shunt at least portion of the feedback current away from the first pnp transistor so as to effect a reduction in the collector and base currents of the first pnp transistor and of the first npn transistor.