Predictive, adaptive power supply for an integrated circuit under test

• US 7,714,603 B2
• Filed: 07/17/2007
• Issued: 05/11/2010
• Est. Priority Date: 01/18/2000
• Status: Expired due to Fees

• Current Assignee: FormFactor Incorporated
• Original Assignee: FormFactor Incorporated
• Inventors: Miller, Charles A., Eldridge, Benjamin N.
• Primary Examiner(s): Hollington; Jermele M
• Application Number:
  US11/779,188
• Publication Number:
  US 20070257696A1
• Time in Patent Office: 1,029 Days
• Field of Search: None
• US Class Current: 324/762.01
• CPC Class Codes: G01R 31/2851 Testing of integrated circuits [IC] G01R31/317 takes precedence; testing individual devices G01R31/26; testing printed circuits G01R31/2801
• CPC Class Codes: G01R 31/31721 Power aspects, e.g. power supplies for test circuits, power saving during test for scan test G01R31/318575
• CPC Class Codes: G01R 31/31905 Interface with the device under test [DUT], e.g. arrangements between the test head and the DUT, mechanical aspects, fixture
• CPC Class Codes: G01R 31/31924 Voltage or current aspects, e.g. driver, receiver
• CPC Class Codes: G06F 1/26 Power supply means, e.g. regulation thereof for memories G11C

Abstract

A main power source supplies current through path impedance to a power terminal of an integrated circuit device under test (DUT). The DUT'"'"'s demand for current at the power input terminal temporarily increases following edges of a clock signal applied to the DUT during a test as transistors within the IC switch in response to the clock signal edges. To limit variation (noise) in voltage at the power input terminal, an auxiliary power supply supplies an additional current pulse to the power input terminal to meet the increased demand during each cycle of the clock signal. The magnitude of the current pulse is a function of a predicted increase in current demand during that clock cycle, and of the magnitude of an adaption signal controlled by a feedback circuit provided to limit variation in voltage developed at the DUT'"'"'s power input terminal.

Claims

1. A testing apparatus for testing a semiconductor device according to a test sequence, comprising:

a tester configured to determine expected input demand at a power terminal of the semiconductor device individually for each cycle of the test sequence for the semiconductor device; and

a power supply coupled to the power terminal of the semiconductor device to supply power to the semiconductor device; and

an adjustment circuit configured to vary the supplied power to the semiconductor device in accordance with the expected input demand during testing of the semiconductor device.

2. The apparatus of claim 1, wherein the expected input demand is different at a first cycle within the test sequence as compared to a second cycle within the test sequence.

3. The apparatus of claim 1, wherein the power supply comprises:

a primary power supply configured to provide a steady supply of power to the power terminal; and

an auxiliary power supply configured to provide a varying supply of power to the power terminal.

4. The apparatus of claim 3, wherein at least part of the adjustment circuit is disposed on a probe card remotely from each of the primary power supply and the auxiliary power supply.

5. The apparatus of claim 3, wherein the adjustment circuit comprises a switch connected at an output of the auxiliary power supply to enable selective connection and disconnection of the auxiliary power supply to the power terminal.

6. The apparatus of claim 1, wherein the power supply further comprises a second adjustment circuit configured to further adjust the supplied power in accordance with an actual input demand at the power terminal.

7. The apparatus of claim 1, wherein the input demand is any one or more of a voltage, a current, and a power.

8. A testing apparatus for testing a semiconductor device according to a test sequence provided by a tester, comprising:

a means for determining expected input demand at a power terminal of the semiconductor device individually for each cycle of a test sequence for the semiconductor device;

a means for testing the semiconductor device in accordance with the test sequence; and

a means for providing varying power to the semiconductor device in accordance with the expected input demand during the testing.

9. The apparatus of claim 8, wherein the expected input demand is different at a first cycle within the test sequence as compared to a second cycle within the test sequence.

10. The apparatus of claim 8, wherein the means for determining determines the expected input demand based on a measurement of an actual power demand of a reference semiconductor for an individual cycle of the test sequence.

11. The apparatus of claim 8, wherein the means for determining determines the expected input demand based on a simulation of a power demand of the semiconductor device for an individual cycle of the test sequence.

12. The apparatus of claim 8, wherein the means for providing varying power comprises:

means for generating a first supply of power to the power terminal; and

means for selectively generating a second supply of power to the power terminal in accordance with the expected input demand.

13. The apparatus of claim 12, further comprising means for controlling the amount of the second supply of power as a function of a cycle of the test sequence.

14. The apparatus of claim 12, further comprising means for controlling the timing of the second supply of power as a function of a cycle of the test sequence.

15. A method of testing a semiconductor device using a test apparatus, comprising:

determining expected input demand at a power terminal of the semiconductor device individually for each cycle of a test sequence for the semiconductor device;

testing the semiconductor device in accordance with the test sequence; and

providing varying power to the semiconductor device in accordance with the expected input demand during the testing.

16. The method of claim 15, wherein the expected input demand is different at a first cycle within the test sequence as compared to a second cycle within the test sequence.

17. The method of claim 15, wherein the determining expected input demand comprises applying signals to a reference semiconductor device in accordance with the test sequence and measuring a power demand of the reference semiconductor for an individual cycle of the test sequence.

18. The method of claim 17, wherein the determining expected input demand comprises applying signals to a reference semiconductor device in accordance with the test sequence and measuring a power demand of the reference semiconductor for each cycle of the test sequence.

19. The method of claim 15, wherein the determining expected input demand comprises simulating a power demand of the semiconductor device for an individual cycle of the test sequence.

20. The method of claim 19, wherein the determining expected input demand comprises simulating a power demand of the semiconductor device for each cycle of the test sequence.

21. The method of claim 15, wherein the providing varying power comprises:

generating a first supply of power to the power terminal; and

selectively generating a second supply of power to the power terminal in accordance with the expected input demand.

22. The method of claim 21, wherein the second supply of power is provided substantially concurrently with an expected increase in demand for current at the power terminal.

23. The method of claim 21, wherein the providing power comprises generating a signal to regulate an amount of the second supply of power provided to the power terminal.

24. The method of claim 21, wherein the providing power comprises generating a signal to regulate a timing of the second supply of power provided to the power terminal.

25. The method of claim 21, wherein the generating a first supply of power is performed by a tester and selectively generating a second supply of power is performed by a probe card.

26. The method of claim 15, wherein the input demand is any one or more of a voltage, a current, and a power.

27. The method of claim 15, further comprising adjusting the power to the semiconductor device based on measurements of actual input demand at the power terminal of the semiconductor device.