Limiter and semiconductor device using the same

• US 7,714,633 B2
• Filed: 04/06/2005
• Issued: 05/11/2010
• Est. Priority Date: 04/09/2004
• Status: Expired due to Fees

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Kato, Kiyoshi
• Primary Examiner(s): LE, DINH THANH
• Application Number:
  US10/593,577
• Publication Number:
  US 20070272759A1
• Time in Patent Office: 1,861 Days
• Field of Search: 327/309, 327/312, 327/321, 327/306, 257/316, 257/360
• US Class Current: 327/309
• CPC Class Codes: G06K 19/07735 the record carrier comprising means for protecting against electrostatic discharge
• CPC Class Codes: G06K 19/07749 the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card
• CPC Class Codes: H01L 23/49855 for flat-cards, e.g. credit cards cards per se G06K19/00
• CPC Class Codes: H01L 27/0266 using field effect transistors as protective elements
• CPC Class Codes: H01L 27/12 the substrate being other than a semiconductor body, e.g. an insulating body
• CPC Class Codes: H01L 27/1214 comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
• CPC Class Codes: H01L 27/1266 the substrate on which the devices are formed not being the final device substrate, e.g. using a temporary substrate
• CPC Class Codes: H01L 27/13 combined with thin-film or thick-film passive components
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/09701 Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/12044 OLED
• CPC Class Codes: H01L 2924/3011 Impedance

Abstract

By using a stacked gate transistor including a floating gate in a limiter, a threshold voltage Vth of the stacked gate transistor can be corrected by controlling the amount of charge accumulated in the floating gate of the stacked gate transistor even in the case where there are variations in the threshold voltage Vth of the stacked gate transistor.

Claims

1. A semiconductor device comprising a limiter,

wherein the limiter includes:

a transistor including a semiconductor layer, a floating gate and a control gate,

wherein the floating gate is formed over the semiconductor layer with a first insulating film interposed therebetween;

the floating gate and the control gate of the transistor overlap each other with a second insulating film interposed therebetween;

a side surface of the floating gate is covered with a third insulating film;

a drain of the transistor is connected to the control gate; and

the drain and the control gate are connected to an input terminal and an output terminal,

wherein the floating gate is electrically floating, and

wherein the limiter is configured to change a limit voltage by controlling an amount of charge accumulated in the floating gate by adjusting a control gate voltage and a source voltage of the transistor.

2. The semiconductor device according to claim 1 further comprising a connecting terminal, wherein the connecting terminal is connected to the drain of the transistor.

3. The semiconductor device according to claim 1 further comprising a resistor, wherein the drain of the transistor is connected to the input terminal through the resistor.

4. The semiconductor device according to claim 1, wherein the transistor is a thin film transistor.

5. A semiconductor device comprising a limiter,

wherein the limiter includes:

a transistor including a semiconductor layer, a floating gate and a control gate,

wherein the floating gate is formed over the semiconductor layer with a first insulating film interposed therebetween;

the floating gate and the control gate of the transistor overlap each other with a second insulating film interposed therebetween;

a side surface of the floating gate is covered with a third insulating film;

a drain of the transistor is connected to the control gate; and

a source of the transistor is connected to an input terminal and an output terminal,

wherein the floating gate is electrically floating, and

wherein the, limiter is configured to chance a limit voltage by controlling an amount of charge accumulated in the floating gate by adjusting a control gate voltage and a source voltage of the transistor.

6. The semiconductor device according to claim 5 further comprising a connecting terminal, wherein the connecting terminal is connected to the source of the transistor.

7. The semiconductor device according to claim 5 further comprising a resistor, wherein the source of the transistor is connected to the input terminal through the resistor.

8. The semiconductor device according to claim 5, wherein the transistor is a thin film transistor.

9. A semiconductor device comprising a limiter,

wherein the limiter includes:

a plurality of transistors each including a semiconductor layer, a floating gate and a control gate,

wherein the floating gate of each of the plurality of transistors is formed over the semiconductor layer of each of the plurality of transistors with a first insulating film interposed therebetween;

the floating gate and the control gate of each of the plurality of transistors overlap each other with a second insulating film interposed therebetween;

a side surface of the floating gate of each of the plurality of transistors is covered with a third insulating film;

a drain of each of the plurality of transistors is connected to the control gate of each of the plurality of transistors;

the plurality of transistors are connected in series so as to have the same forward current direction; and

the drain and the control gate of one of the plurality of transistors are connected to an input terminal and an output terminal,

wherein the floating gate of each of the plurality of transistors is electrically floating, and

wherein the limiter is configured to change a limit voltage by controlling an amount of charge accumulated in at least one of the floating gates by adjusting a control gate voltage and a source voltage of at least one of the transistors.

10. The semiconductor device according to claim 9 further comprising a connecting terminal, wherein the connecting terminal is connected to the drain of the one of the plurality of transistors.

11. The semiconductor device according to claim 9 further comprising a resistor, wherein the drain of the one of the plurality of transistors is connected to the input terminal through the resistor.

12. The semiconductor device according to claim 9, wherein the plurality of transistors are thin film transistors.

13. A semiconductor device comprising a limiter,

wherein the limiter includes:

a plurality of transistors each including a semiconductor layer, a floating gate and a control gate,

wherein the floating gate of each of the plurality of transistors is formed over the semiconductor layer of each of the plurality of transistors with a first insulating film interposed therebetween;

the floating gate and the control gate of each of the plurality of transistors overlap each other with a second insulating film interposed therebetween;

a side surface of the floating gate of each of the plurality of transistors is covered with a third insulating film;

a drain of each of the plurality of transistors is connected to the control gate of each of the plurality of transistors;

the plurality of transistors are connected in series so as to have the same forward current direction; and

a source of one of the plurality of transistors is connected to an input terminal and an output terminal,

wherein the floating gate of each of the plurality of transistors is electrically floating, and

wherein the limiter is configured to change a limit voltage by controlling an amount of charge accumulated in at least one of the floating gates by adjusting a control gate voltage and a source voltage of at least one of the transistors.

14. The semiconductor device according to claim 13 further comprising a connecting terminal, wherein the connecting terminal is connected to the source of the one of the plurality of transistors.

15. The semiconductor device according to claim 13 further comprising a resistor, wherein the source of the one of the plurality of transistors is connected to the input terminal through the resistor.

16. The semiconductor device according to claim 13, wherein the plurality of transistors are thin film transistors.

17. A semiconductor device comprising a limiter,

wherein the limiter includes:

a first transistor, and

a second transistor,

wherein a floating gate of the first transistor is formed over a semiconductor layer of the first transistor with a first insulating film interposed therebetween;

the floating gate and a control gate of the first transistor overlap each other with a second insulating film interposed therebetween;

a side surface of the floating gate of the first transistor is covered with a third insulating film;

a drain of the first transistor is connected to the control gate of the first transistor;

a drain of the second transistor is connected to a gate of the second transistor;

the first transistor and the second transistor are connected in series so as to have the same forward current direction; and

the drain of the second transistor and the control gate are connected to an input terminal and an output terminal,

wherein the floating gate of the first transistor is electrically floating, and

wherein the limiter is configured to change a limit voltage by controlling an amount of charge accumulated in the floating gate by adjusting a control gate voltage and a source voltage of the first transistor.

18. The semiconductor device according to claim 17 further comprising a connecting terminal, wherein the connecting terminal is connected to the drain of the second transistor.

19. The semiconductor device according to claim 17 further comprising a resistor, wherein the drain of the second transistor is connected to the input terminal through the resistor.

20. The semiconductor device according to claim 17, wherein the second transistor is a thin film transistor.

21. A semiconductor device comprising a limiter,

wherein the limiter includes:

a first transistor, and

a second transistor,

wherein a floating gate of the first transistor is formed over a semiconductor layer of the first transistor with a first insulating film interposed therebetween;

the floating gate and a control gate of the first transistor overlap each other with a second insulating film interposed therebetween;

a side surface of the floating gate of the first transistor is covered with a third insulating film;

a drain of the second transistor is connected to a gate of the second transistor;

the first transistor and the second transistor are connected in series so as to have the same forward current direction; and

a source of the second transistor is connected to an input terminal and an output terminal,

wherein the floating gate of the first transistor is electrically floating, and

wherein the limiter is configured to change a limit voltage by controlling an amount of charge accumulated in the floating gate by adjusting a control gate voltage and a source voltage of the first transistor.

22. The semiconductor device according to claim 21 further comprising a connecting terminal, wherein the connecting terminal is connected to the source of the second transistor.

23. The semiconductor device according to claim 21 further comprising a resistor, wherein the source of the second transistor is connected to the input terminal through the resistor.

24. The semiconductor device according to claim 21, wherein the second transistor is a thin film transistor.

25. A semiconductor device comprising:

an integrated circuit, and

an antenna connected to the integrated circuit,

wherein the integrated circuit includes a limiter;

the limiter includes a transistor;

a floating gate of the transistor is formed over a semiconductor layer of the transistor with a first insulating film interposed therebetween;

the floating gate and a control gate of the transistor overlap each other with a second insulating film interposed therebetween;

a side surface of the floating gate is covered with a third insulating film;

a drain of the transistor is connected to the control gate; and

the drain and the control gate are connected to an input terminal and an output terminal,

wherein the floating gate is electrically floating, and

wherein the limiter is configured to change a limit voltage by controlling an amount of charge accumulated in the floating gate by adjusting a control gate voltage and a source voltage of the transistor.

27. The semiconductor device according to claim 25 or 26 further comprising a resistor, wherein the drain of the transistor is connected to the input terminal through the resistor.

28. The semiconductor device according to claim 25 or 26, wherein the transistor is a thin film transistor.

26. A semiconductor device comprising an integrated circuit and an antenna connected to the integrated circuit,

wherein the integrated circuit includes a limiter, a pulse generation circuit for controlling a limit voltage of the limiter, and a booster circuit for supplying a power supply voltage to the pulse generation circuit;

the limiter includes a transistor;

a floating gate of the transistor is formed over a semiconductor layer of the transistor with a first insulating film interposed therebetween;

the floating gate and a control gate of the transistor overlap each other with a second insulating film interposed therebetween;

a side surface of the floating gate is covered with a third insulating film;

a drain of the transistor is connected to the control gate; and

the drain and the control gate are connected to an input terminal and an output terminal;

wherein the floating gate is electrically floating, and

wherein the limiter is configured to change the limit voltage by controlling an amount of charge accumulated in the floating gate by adjusting a control gate voltage and a source voltage of the transistor.