Transflective liquid crystal display device and method of fabricating the same

• US 7,714,963 B2
• Filed: 03/10/2006
• Issued: 05/11/2010
• Est. Priority Date: 09/09/2005
• Status: Expired due to Fees

• Current Assignee: LG Display Co., Ltd.
• Original Assignee: LG Display Co., Ltd.
• Inventors: Yang, Joon Young, Lee, Jung Il
• Primary Examiner(s): RUDE, TIMOTHY L
• Application Number:
  US11/372,081
• Publication Number:
  US 20070058116A1
• Time in Patent Office: 1,523 Days
• Field of Search: None
• US Class Current: 349/114
• CPC Class Codes: G02F 1/133371 Cells with varying thickness of the liquid crystal layer
• CPC Class Codes: G02F 1/133555 Transflectors
• CPC Class Codes: G02F 1/13439 characterised by their electrical, optical, physical properties; materials therefor; method of making
• CPC Class Codes: G02F 1/136231 for reducing the number of lithographic steps
• CPC Class Codes: G02F 2201/123 pixel
• CPC Class Codes: G02F 2203/02 reflective

Abstract

An array substrate for a transflective liquid crystal display device includes: a substrate; a gate line and a data line on the substrate, the gate line and the data line crossing each other to define a pixel region including a transmissive area and a reflective area surrounding the transmissive area; a thin film transistor having a gate insulating layer, the thin film transistor electrically connected to the gate line and the data line; a first passivation layer having a drain contact hole exposing a drain electrode of the thin film transistor and a through hole exposing the substrate in the transmissive area; a pixel electrode on the first passivation layer, the pixel electrode contacting the substrate in the transmissive area through the through hole; and a reflective plate on the pixel electrode, the reflective plate being electrically connected to the drain electrode through the drain contact hole and to the pixel electrode.

Claims

1. An array substrate for a transflective liquid crystal display

device, comprising:

a substrate;

a gate line and a data line on the substrate, the gate line and the data line crossing each other to define a pixel region including a transmissive area and a reflective area surrounding the transmissive area;

a thin film transistor having a gate insulating layer, the thin film transistor electrically connected to the gate line and the data line

a first passivation layer on the thin film transistor, the first passivation layer having a drain contact hole exposing a drain electrode of the thin film transistor and a through hole exposing the substrate in the transmissive area;

a second passivation layer of an inorganic insulating material between the thin film transistor and the first passivation layer, wherein the second passivation layer has the drain contact hole exposing the drain electrode;

a third passivation layer of an inorganic insulating material between the first passivation layer and the reflective plate, wherein the third passivation layer has the drain contact hole exposing the drain electrode;

a pixel electrode on the first passivation layer, the pixel electrode contacting the substrate in the transmissive area through the through hole;

a reflective plate on the pixel electrode, the reflective plate being electrically connected to the drain electrode through the drain contact hole and to the pixel electrode; and

a drain terminal of a transparent conductive material positioned between the reflective plate and the drain electrode,

wherein the drain terminal is formed of the same layer as the pixel electrode and patterned apart from the pixel electrode, and

wherein the reflective plate is electrically connected to the drain electrode through the drain terminal.

2. The array substrate according to claim 1, further comprising a storage capacitor electrically connected to the reflective plate, wherein the storage capacitor includes a first storage electrode that is a portion of the gate line, a portion of the gate insulating layer on the first storage electrode and a second storage electrode on the gate insulating layer.

3. The array substrate according to claim 2, wherein the first passivation layer has a storage contact hole exposing the second storage electrode, and the reflective plate is electrically connected to the second storage electrode through the storage contact hole.

4. The array substrate according to claim 3, further comprising a storage terminal of a transparent conductive material between the reflective plate and the second storage electrode.

5. The array substrate according to claim 4, wherein the storage terminal is formed of the same layer as the pixel electrode.

6. The array substrate according to claim 1, wherein the pixel electrode is formed on a bottom and a sidewall of the through hole, and wherein the reflective plate electrically contacts the pixel electrode on the sidewall of the through hole and exposes the pixel electrode on the bottom of the through hole.

7. The array substrate according to claim 1, further comprising a gate pad at one end of the gate line and a data pad at one end of the data line.

8. The array substrate according to claim 7, further comprising a gate pad terminal on the gate pad and a data pad terminal on the data pad, wherein the gate pad terminal and the data pad terminal are formed of a transparent conductive material.

9. The array substrate according to claim 8, wherein gate pad terminal and the data pad terminal is formed of the same layer as the pixel electrode.

10. The array substrate according to claim 1, wherein the first passivation layer is formed of an organic insulating material and has an uneven top surface.

11. The array substrate according to claim 10, wherein the reflective plate has an embossed shape corresponding to the uneven top surface of the first passivation layer.

12. The array substrate according to claim 1, wherein the thin film transistor includes a gate electrode, a gate insulating layer on the gate electrode, an active layer on the gate insulating layer over the gate electrode, an ohmic contact layer on the active layer, a source electrode on the ohmic contact layer, the drain electrode spaced apart from the source electrode.