Direct memory access controller with encryption and decryption for non-blocking high bandwidth I/O transactions

• US 7,716,389 B1
• Filed: 03/17/2006
• Issued: 05/11/2010
• Est. Priority Date: 03/17/2006
• Status: Active Grant

• Current Assignee: BiTMICRO, LLC (BiTMICRO Networks, Inc.)
• Original Assignee: BiTMICRO Networks, Inc.
• Inventors: Bruce, Rey, David, Raquel Bautista, Estrada, Shielou Vicencio
• Primary Examiner(s): PEYTON, TAMMARA R
• Application Number:
  US11/378,762
• Time in Patent Office: 1,516 Days
• Field of Search: 710/1, 710/22, 710/110, 370/338, 370/392, 370/466, 380/255, 380/277
• US Class Current: 710/22
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence

Abstract

Due to the integration of multiple I/O device controllers in a storage controller and the need to provide secure and fast data transfers between the I/O devices and the storage controller, an architecture that can perform multiple encrypt/decrypt operations simultaneously is therefore needed to service multiple transfer requests without a negative impact on the speed of transfer and processing. The present invention relates to enhancing Direct Memory Access (DMA) operations between multiple IO devices and a storage controller by adding a Data Processing Core. Exemplary implementations are provided to illustrate the background mechanism used by a DMA controller that minimizes central-processing-unit (CPU) intervention and the multi-channel architecture which allows multiple IO requests to be serviced simultaneously.

Claims

1. A computer-enabled method for data processing enhanced DMA data transfers to or from a memory, the method comprising:

performing a DMA data transfer using one or more DMA engines;

determining one or more DPC hit signals;

performing data processing using one or more DPC channels in response to said determining one or more DPC hit signals;

configuring the one or more DMA engines according to one or more DMA descriptor tables; and

configuring the one or more DPC channels according to one or more DPC descriptor tables;

reading a DPC Enable and a DPC Index from the one or more DMA descriptor tables;

using the DPC Enable to determine whether to perform data processing; and

using the DPC Index to determine if a DPC Channel is assigned.

2. The method of claim 1, wherein the determining one or more DPC hit signals includes comparing one or more DMA addresses with one or more DPC channel address ranges.

3. The method of claim 1, wherein the one or more DPC channels intercepts one or more DMA data for data processing.

4. The method of claim 1, further includes synchronizing the one or more DMA engines and the one or more DPC channels, said synchronizing includes using a DPC Dependency Checking protocol.

5. The method of claim 4, wherein said using a DPC Dependency Checking protocol includes using a DPC request and a DPC acknowledge.

6. The method of claim 1, further includes using a scatter gather list from the one or more DMA descriptor tables.

7. A computer-enabled method for data processing enhanced DMA data transfers to or from a memory, the method comprising the steps of:

performing a DMA data transfer using one or more DMA engines;

determining one or more DPC hit signals;

performing data processing using one or more DPC channels in response to the determining of one or more DPC hit signals;

configuring the one or more DMA engines according to one or more DMA descriptor tables;

configuring the one or more DPC channels according to one or more DPC descriptor tables;

obtaining a DPC Setting from the one or more DPC descriptor tables; and

wherein one or more encryption algorithms, one or more encryption key sizes and one or more cipher modes to be used by one or more DPC Engines for data processing is determined.

8. The method of claim 7, further includes using a scatter gather list from the one or more DPC descriptor tables.

9. The method of claim 7, wherein the one or more DPC engines performs encryption or decryption of one or more DMA data based on the DPC Setting.

10. A computer-enabled apparatus for data processing enhanced DMA data transfers to or from a memory, comprising:

a means for performing DMA data transfers, said means for performing DMA transfers disposed to use one or more DMA engines;

a means for performing data processing, said means for performing data processing disposed to use one or more DPC channels and to respond to one or more DPC hit signals;

a processing device disposed to configure one or more DMA engines according to one or more DMA descriptor tables;

said processing device further disposed to configure one or more DPC channels according to one or more DPC descriptor tables;

wherein the one or more DMA descriptor tables comprises a DPC Enable and a DPC Index;

wherein the means for performing data processing is further disposed to use the DPC Enable to determine whether to perform data processing; and

wherein the means for performing data processing is further disposed to use the DPC Index to determine which of the one or more DPC Channels are assigned.

11. The apparatus of claim 10, further including an address compare engine disposed to compare one or more DMA addresses with one or more DPC channel address ranges.

12. The apparatus of claim 10, wherein the one or more DPC channels is disposed to intercept one or more DMA data for data processing.

13. The apparatus of claim 10, wherein the one or more DMA engines and the one or more DPC channels are disposed to use a DPC Dependency Checking protocol for synchronization.

14. The apparatus of claim 10, wherein the DPC Dependency Checking protocol comprises a DPC request and a DPC acknowledge.

15. The apparatus of claim 10, wherein the one or more DMA descriptor tables comprises a scatter gather list.

16. The apparatus of claim 10, wherein the one or more DPC descriptor tables comprises a scatter gather list.

17. A computer-enabled apparatus for data processing enhanced DMA data transfers to or from a memory, comprising:

a means for performing DMA data transfers, said means for performing DMA transfers disposed to use one or more DMA engines;

a means for performing data processing, said means for performing data processing disposed to use one or more DPC channels and to respond to one or more DPC hit signals;

a processing device disposed to configure one or more DMA engines according to one or more DMA descriptor tables;

said processing device further disposed to configure one or more DPC channels according to one or more DPC descriptor tables;

wherein the one or more DPC descriptor tables comprises a DPC Setting; and

the DPC Setting including information that specifies at least one encryption algorithm, at least one encryption key size, and at least one cipher mode to be used by at least one DPC Engine for data processing.

18. The apparatus of claim 17, wherein the one or more DPC engines are disposed to perform encryption or decryption of one or more DMA data based on the DPC Setting.

19. A direct memory access controller for transferring data to or from a memory, and for encrypting or decrypting said data upon receiving a data processing request, the direct memory access controller comprising:

a means for performing a DMA data transfer, said means for performing a DMA data transfer including at least one DMA engine configured for transferring data;

a means for performing data processing coupled to said means for performing a DMA data transfer, said data processing includes encrypting or decrypting said data in response to a DPC hit signal by at least using a DPC channel to intercept said data, causing said data to be transferred to said means for performing data processing.

20. The direct memory access controller of claim 19, wherein said DPC hit signal is asserted if one or more DMA addresses is determined to be within a DPC channel address range.

21. The direct memory access controller of claim 20, wherein:

said at least one DMA engine is configured by at least using a DMA descriptor table that includes a DPC Enable for causing said means for performing data processing to encrypt or decrypt said data; and

said DPC channel is configured by at least using a DPC descriptor table.

22. The direct memory access controller of claim 19, wherein said means for data processing is disposed not to process said data if said data is not intercepted.

23. The direct memory access controller of claim 19, wherein if said DPC channel is not used to intercept said data, said data processing does not include encrypting or decrypting said data.